[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30054 )
Change subject: mem: Add a header latency parameter to the XBar
..
mem: Add a header latency parameter to the XBar
The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.
Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30054
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M src/mem/XBar.py
M src/mem/coherent_xbar.cc
M src/mem/xbar.cc
M src/mem/xbar.hh
4 files changed, 15 insertions(+), 7 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index deed98f..84aae99 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -68,6 +68,11 @@
forward_latency = Param.Cycles("Forward latency")
response_latency = Param.Cycles("Response latency")
+# The XBar uses one Layer per master. Each Layer forwards a packet
+# to its destination and is occupied for header_latency + size /
+# width cycles
+header_latency = Param.Cycles(1, "Header latency")
+
# Width governing the throughput of the crossbar
width = Param.Unsigned("Datapath width per port (bytes)")
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 952bd41..7fb9c34 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -180,7 +180,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// is this the destination point for this packet? (e.g. true if
// this xbar is the PoC for a cache maintenance operation to the
@@ -471,7 +471,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
if (snoopFilter && !system->bypassCaches()) {
// let the snoop filter inspect the response and update its state
@@ -619,7 +619,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// forward it either as a snoop response or a normal response
if (forwardAsSnoop) {
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9920216..f0b4ba3 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
frontendLatency(p->frontend_latency),
forwardLatency(p->forward_latency),
responseLatency(p->response_latency),
+ headerLatency(p->header_latency),
width(p->width),
gotAddrRanges(p->port_default_connection_count +
p->port_master_connection_count, false),
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74..086d7f4 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -307,6 +307,8 @@
const Cycles frontendLatency;
const Cycles forwardLatency;
const Cycles responseLatency;
+/** Cycles the layer is occupied processing the packet header */
+const Cycles headerLatency;
/** the width of the xbar in bytes */
const uint32_t width;
--
To view, visit https://
[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30054 )
Change subject: mem: Add a header latency parameter to the XBar
..
mem: Add a header latency parameter to the XBar
The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.
Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris
---
M src/mem/XBar.py
M src/mem/coherent_xbar.cc
M src/mem/xbar.cc
M src/mem/xbar.hh
4 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index deed98f..84aae99 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -68,6 +68,11 @@
forward_latency = Param.Cycles("Forward latency")
response_latency = Param.Cycles("Response latency")
+# The XBar uses one Layer per master. Each Layer forwards a packet
+# to its destination and is occupied for header_latency + size /
+# width cycles
+header_latency = Param.Cycles(1, "Header latency")
+
# Width governing the throughput of the crossbar
width = Param.Unsigned("Datapath width per port (bytes)")
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 952bd41..7fb9c34 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -180,7 +180,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// is this the destination point for this packet? (e.g. true if
// this xbar is the PoC for a cache maintenance operation to the
@@ -471,7 +471,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
if (snoopFilter && !system->bypassCaches()) {
// let the snoop filter inspect the response and update its state
@@ -619,7 +619,7 @@
calcPacketTiming(pkt, xbar_delay);
// determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
// forward it either as a snoop response or a normal response
if (forwardAsSnoop) {
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9920216..f0b4ba3 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
frontendLatency(p->frontend_latency),
forwardLatency(p->forward_latency),
responseLatency(p->response_latency),
+ headerLatency(p->header_latency),
width(p->width),
gotAddrRanges(p->port_default_connection_count +
p->port_master_connection_count, false),
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74..086d7f4 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -307,6 +307,8 @@
const Cycles frontendLatency;
const Cycles forwardLatency;
const Cycles responseLatency;
+/** Cycles the layer is occupied processing the packet header */
+const Cycles headerLatency;
/** the width of the xbar in bytes */
const uint32_t width;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I12752ab4415617
