[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Add a setThreadContext method to the ISA class.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29233 )
Change subject: arch,cpu: Add a setThreadContext method to the ISA class.
..
arch,cpu: Add a setThreadContext method to the ISA class.
Also remove ThreadContext pointer parameters to some of the methods in
the ISA classes.
Change-Id: I8e502b1857d299cb2e759a9734a1df4f65f31efe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29233
Reviewed-by: Brandon Potter
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/power/isa.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/ua2005.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/cpu/SConscript
M src/cpu/base.cc
D src/cpu/cpuevent.cc
D src/cpu/cpuevent.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/cpu.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
26 files changed, 243 insertions(+), 600 deletions(-)
Approvals:
Brandon Potter: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 9c686f6..9966b9e 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1171,7 +1171,7 @@
ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
{
auto *isa = static_cast(tc->getIsaPtr());
-return isa->getCurSveVecLenInBits(tc);
+return isa->getCurSveVecLenInBits();
}
}
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b3ea91e..29c5538 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -120,19 +120,16 @@
}
void
-ISA::clear(ThreadContext *tc)
-{
-clear();
-// Invalidate cached copies of miscregs in the TLBs
-getITBPtr(tc)->invalidateMiscReg();
-getDTBPtr(tc)->invalidateMiscReg();
-}
-
-void
ISA::clear()
{
const Params *p(params());
+// Invalidate cached copies of miscregs in the TLBs
+if (tc) {
+getITBPtr(tc)->invalidateMiscReg();
+getDTBPtr(tc)->invalidateMiscReg();
+}
+
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
memset(miscRegs, 0, sizeof(miscRegs));
@@ -421,31 +418,40 @@
}
void
-ISA::startup(ThreadContext *tc)
+ISA::startup()
{
-pmu->setThreadContext(tc);
+BaseISA::startup();
-if (system) {
-Gicv3 *gicv3 = dynamic_cast(system->getGIC());
-if (gicv3) {
-
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(tc);
-}
-}
+if (tc)
+setupThreadContext();
afterStartup = true;
}
void
+ISA::setupThreadContext()
+{
+pmu->setThreadContext(tc);
+
+if (!system)
+return;
+
+Gicv3 *gicv3 = dynamic_cast(system->getGIC());
+if (!gicv3)
+return;
+
+if (!gicv3CpuInterface)
+gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+gicv3CpuInterface->setISA(this);
+gicv3CpuInterface->setThreadContext(tc);
+}
+
+void
ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
{
-pmu->setThreadContext(new_tc);
-
-if (system && gicv3CpuInterface) {
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(new_tc);
-}
+tc = new_tc;
+setupThreadContext();
}
RegVal
@@ -473,7 +479,7 @@
RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+ISA::readMiscReg(int misc_reg)
{
CPSR cpsr = 0;
PCState pc = 0;
@@ -760,12 +766,12 @@
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
-return getGenericTimer(tc).readMiscReg(misc_reg);
+return getGenericTimer().readMiscReg(misc_reg);
case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
-return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
+return getGICv3CPUInterface().readMiscReg(misc_reg);
default:
break;
@@ -797,7 +803,7 @@
}
void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val)
{
RegVal newVal = val;
@@ -827,7 +833,7 @@
pc.nextJazelle(cpsr.j);
pc.illegalExec(cpsr.il == 1);
-tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) -
1);
+tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
// Follow slightly different semantics if a CheckerCPU object
[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Add a setThreadContext method to the ISA class.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/29233 )
Change subject: arch,cpu: Add a setThreadContext method to the ISA class.
..
arch,cpu: Add a setThreadContext method to the ISA class.
Also remove ThreadContext pointer parameters to some of the methods in
the ISA classes.
Change-Id: I8e502b1857d299cb2e759a9734a1df4f65f31efe
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/power/isa.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/ua2005.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/cpu/SConscript
M src/cpu/base.cc
D src/cpu/cpuevent.cc
D src/cpu/cpuevent.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/cpu.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
26 files changed, 243 insertions(+), 597 deletions(-)
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 70e5fb9..95aa090 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1169,7 +1169,7 @@
ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
{
auto *isa = static_cast(tc->getIsaPtr());
-return isa->getCurSveVecLenInBits(tc);
+return isa->getCurSveVecLenInBits();
}
}
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b18bbb0..03a7cf1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -120,19 +120,16 @@
}
void
-ISA::clear(ThreadContext *tc)
-{
-clear();
-// Invalidate cached copies of miscregs in the TLBs
-getITBPtr(tc)->invalidateMiscReg();
-getDTBPtr(tc)->invalidateMiscReg();
-}
-
-void
ISA::clear()
{
const Params *p(params());
+// Invalidate cached copies of miscregs in the TLBs
+if (tc) {
+getITBPtr(tc)->invalidateMiscReg();
+getDTBPtr(tc)->invalidateMiscReg();
+}
+
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
memset(miscRegs, 0, sizeof(miscRegs));
@@ -421,31 +418,40 @@
}
void
-ISA::startup(ThreadContext *tc)
+ISA::startup()
{
-pmu->setThreadContext(tc);
+BaseISA::startup();
-if (system) {
-Gicv3 *gicv3 = dynamic_cast(system->getGIC());
-if (gicv3) {
-
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(tc);
-}
-}
+if (tc)
+setupThreadContext();
afterStartup = true;
}
void
+ISA::setupThreadContext()
+{
+pmu->setThreadContext(tc);
+
+if (!system)
+return;
+
+Gicv3 *gicv3 = dynamic_cast(system->getGIC());
+if (!gicv3)
+return;
+
+if (!gicv3CpuInterface)
+gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+gicv3CpuInterface->setISA(this);
+gicv3CpuInterface->setThreadContext(tc);
+}
+
+void
ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
{
-pmu->setThreadContext(new_tc);
-
-if (system && gicv3CpuInterface) {
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(new_tc);
-}
+tc = new_tc;
+setupThreadContext();
}
RegVal
@@ -473,7 +479,7 @@
RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+ISA::readMiscReg(int misc_reg)
{
CPSR cpsr = 0;
PCState pc = 0;
@@ -760,12 +766,12 @@
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
-return getGenericTimer(tc).readMiscReg(misc_reg);
+return getGenericTimer().readMiscReg(misc_reg);
case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
-return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
+return getGICv3CPUInterface().readMiscReg(misc_reg);
default:
break;
@@ -797,7 +803,7 @@
}
void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val)
{
RegVal newVal = val;
@@ -827,7 +833,7 @@
pc.nextJazelle(cpsr.j);
pc.illegalExec(cpsr.il == 1);
-tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) -
1);
+tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
// Follow slightly different semantics if a CheckerCPU object
// is connected
@@ -1132,8 +1138,8 @@
// TLB Invalidate All
case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
{
-assert32(tc);
-scr = readMiscReg(MISCREG_SCR, tc);
+assert32();
