[gem5-dev] Change in gem5/gem5[develop]: arch: Add a mechanism to pad the src or dest reg index arrays.

2021-01-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38380 )


Change subject: arch: Add a mechanism to pad the src or dest reg index  
arrays.

..

arch: Add a mechanism to pad the src or dest reg index arrays.

ARM reaches in and pads out the source register index list behind the
parser's back to force dest regs to also be sources in case an
instruction fails predication and needs to forward the original register
values. It shouldn't be hacking up these values in that way, but since
it is, this will let it continue to do so while still fitting in the new
system where each instruction allocates its src/dest reg index arrays to
size.

Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38380
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 11 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index ff54889..9ca813e 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -107,7 +107,8 @@

 myDict['reg_idx_arr_decl'] = \
 'RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]' % \
-(d.operands.numSrcRegs, d.operands.numDestRegs)
+(d.operands.numSrcRegs + d.srcRegIdxPadding,
+ d.operands.numDestRegs + d.destRegIdxPadding)

 # The reinterpret casts are largely because an array with a  
known
 # size cannot be passed as an argument which is an array with  
an

@@ -391,6 +392,9 @@

 self.operands = OperandList(parser, compositeCode)

+self.srcRegIdxPadding = 0
+self.destRegIdxPadding = 0
+
 # The header of the constructor declares the variables to be used
 # in the body of the constructor.
 header = ''
@@ -464,6 +468,12 @@
 else:
 self.fp_enable_check = ''

+def padSrcRegIdx(self, padding):
+self.srcRegIdxPadding = padding
+
+def padDestRegIdx(self, padding):
+self.destRegIdxPadding = padding
+

 ###
 #

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38380
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Gerrit-Change-Number: 38380
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch: Add a mechanism to pad the src or dest reg index arrays.

2020-12-07 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38380 )



Change subject: arch: Add a mechanism to pad the src or dest reg index  
arrays.

..

arch: Add a mechanism to pad the src or dest reg index arrays.

ARM reaches in and pads out the source register index list behind the
parser's back to force dest regs to also be sources in case an
instruction fails predication and needs to forward the original register
values. It shouldn't be hacking up these values in that way, but since
it is, this will let it continue to do so while still fitting in the new
system where each instruction allocates its src/dest reg index arrays to
size.

Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 11 insertions(+), 1 deletion(-)



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index ff54889..9ca813e 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -107,7 +107,8 @@

 myDict['reg_idx_arr_decl'] = \
 'RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]' % \
-(d.operands.numSrcRegs, d.operands.numDestRegs)
+(d.operands.numSrcRegs + d.srcRegIdxPadding,
+ d.operands.numDestRegs + d.destRegIdxPadding)

 # The reinterpret casts are largely because an array with a  
known
 # size cannot be passed as an argument which is an array with  
an

@@ -391,6 +392,9 @@

 self.operands = OperandList(parser, compositeCode)

+self.srcRegIdxPadding = 0
+self.destRegIdxPadding = 0
+
 # The header of the constructor declares the variables to be used
 # in the body of the constructor.
 header = ''
@@ -464,6 +468,12 @@
 else:
 self.fp_enable_check = ''

+def padSrcRegIdx(self, padding):
+self.srcRegIdxPadding = padding
+
+def padDestRegIdx(self, padding):
+self.destRegIdxPadding = padding
+

 ###
 #

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38380
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Gerrit-Change-Number: 38380
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s