[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.
Nils Asmussen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25645 )
Change subject: arch-riscv: added support for pseudo instructions.
..
arch-riscv: added support for pseudo instructions.
Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25645
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
A src/arch/riscv/insts/pseudo.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/formats.isa
A src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/operands.isa
M src/arch/riscv/utility.hh
8 files changed, 126 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
new file mode 100644
index 000..47b11ad
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
+#define __ARCH_RISCV_INSTS_PSEUDO_HH__
+
+#include
+
+#include "arch/riscv/insts/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class PseudoOp : public RiscvStaticInst
+{
+ protected:
+using RiscvStaticInst::RiscvStaticInst;
+
+std::string generateDisassembly(
+Addr pc, const SymbolTable *symtab) const override
+{
+return mnemonic;
+}
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/bitfields.isa
b/src/arch/riscv/isa/bitfields.isa
index dae7fe1..e32c82d 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -119,3 +120,6 @@
def bitfield CIMM3 <12:10>;
def bitfield CIMM2 <6:5>;
def bitfield CIMM1 <12>;
+
+// Pseudo instructions
+def bitfield M5FUNC <31:25>;
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 63cf1e4..4f8fea2 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -1832,5 +1833,7 @@
}}, IsNonSpeculative, No_OpClass);
}
}
+
+0x1e: M5Op::M5Op();
}
}
diff --git a/src/arch/riscv/isa/formats/formats.isa
b/src/arch/riscv/isa/formats/formats.isa
index 0f7dc42..2a6b910 100644
--- a/src/arch/riscv/isa/formats/formats.isa
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25645 )
Change subject: arch-riscv: added support for pseudo instructions.
..
arch-riscv: added support for pseudo instructions.
Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/pseudo.cc
A src/arch/riscv/insts/pseudo.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/formats.isa
A src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/operands.isa
8 files changed, 445 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index d9e47c3..8e292f1 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,5 +1,6 @@
# Copyright (c) 2015 RISC-V Foundation
# Copyright (c) 2017 The University of Virginia
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -31,5 +32,6 @@
Source('amo.cc')
Source('compressed.cc')
Source('mem.cc')
+Source('pseudo.cc')
Source('standard.cc')
Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/pseudo.cc b/src/arch/riscv/insts/pseudo.cc
new file mode 100644
index 000..e0a1b4d
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.cc
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/insts/pseudo.hh"
+
+#include
+#include
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+PseudoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+return mnemonic;
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
new file mode 100644
index 000..3c19d87
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
