[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.
Nils Asmussen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25657 )
Change subject: arch-riscv: let FPU instructions fault if status.FS = off.
..
arch-riscv: let FPU instructions fault if status.FS = off.
These checks are required for some tests in the RISC-V test suite.
However, actually we also need to set the INITIAL/CLEAN/DIRTY flags
accordingly, which is not done yet.
Change-Id: If5d6ac22069b51a57b6353cd6d45b77ee51a4d55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25657
Tested-by: kokoro
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
3 files changed, 43 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index c56c45b..a6c77ce 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -60,6 +60,14 @@
PRV_M = 3
};
+enum FPUStatus
+{
+OFF = 0,
+INITIAL = 1,
+CLEAN = 2,
+DIRTY = 3,
+};
+
class ISA : public BaseISA
{
protected:
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 35d08ec..7b19464 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -50,6 +50,11 @@
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Fp2_bits = Mem;
}}, {{
EA = Rp1 + offset;
@@ -75,6 +80,11 @@
0x5: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Mem = Fp2_bits;
}}, {{
EA = Rp1 + offset;
@@ -390,9 +400,19 @@
0x01: decode FUNCT3 {
format Load {
0x2: flw({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Fd_bits = (uint64_t)Mem_uw;
}}, inst_flags=FloatMemReadOp);
0x3: fld({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Fd_bits = Mem;
}}, inst_flags=FloatMemReadOp);
}
@@ -484,9 +504,19 @@
0x09: decode FUNCT3 {
format Store {
0x2: fsw({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Mem_uw = (uint32_t)Fs2_bits;
}}, inst_flags=FloatMemWriteOp);
0x3: fsd({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Mem_ud = Fs2_bits;
}}, inst_flags=FloatMemWriteOp);
}
diff --git a/src/arch/riscv/isa/formats/fp.isa
b/src/arch/riscv/isa/formats/fp.isa
index e383db8..389b5cf 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 Riscv Developers
// Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -37,6 +38,10 @@
{
Fault fault = NoFault;
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+fault = make_shared("FPU is off", machInst);
+
%(op_decl)s;
%(op_rd)s;
if (fault == NoFault) {
--
To view, visit https://ge
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25657 )
Change subject: arch-riscv: let FPU instructions fault if status.FS = off.
..
arch-riscv: let FPU instructions fault if status.FS = off.
These checks are required for some tests in the RISC-V test suite.
However, actually we also need to set the INITIAL/CLEAN/DIRTY flags
accordingly, which is not done yet.
Change-Id: If5d6ac22069b51a57b6353cd6d45b77ee51a4d55
---
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
3 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index c56c45b..73df087 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -60,6 +60,14 @@
PRV_M = 3
};
+enum FSMode
+{
+OFF = 0,
+INITIAL = 1,
+CLEAN = 2,
+DIRTY = 3,
+};
+
class ISA : public BaseISA
{
protected:
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f0a90a..ad19393 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -50,6 +50,11 @@
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Fp2_bits = Mem;
}}, {{
EA = Rp1 + offset;
@@ -75,6 +80,11 @@
0x5: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Mem = Fp2_bits;
}}, {{
EA = Rp1 + offset;
@@ -390,9 +400,19 @@
0x01: decode FUNCT3 {
format Load {
0x2: flw({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Fd_bits = (uint64_t)Mem_uw;
}}, inst_flags=FloatMemReadOp);
0x3: fld({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Fd_bits = Mem;
}}, inst_flags=FloatMemReadOp);
}
@@ -484,9 +504,19 @@
0x09: decode FUNCT3 {
format Store {
0x2: fsw({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Mem_uw = (uint32_t)Fs2_bits;
}}, inst_flags=FloatMemWriteOp);
0x3: fsd({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+ machInst);
+
Mem_ud = Fs2_bits;
}}, inst_flags=FloatMemWriteOp);
}
diff --git a/src/arch/riscv/isa/formats/fp.isa
b/src/arch/riscv/isa/formats/fp.isa
index e383db8..cb2a90c 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 Riscv Developers
// Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -37,6 +38,10 @@
{
Fault fault = NoFault;
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off", machInst);
+
%(op_decl)s;
%(op_rd)s;
if (fault == NoFault) {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25657
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If5d6ac22069b51a57b6353cd6d45b77ee51a4d55
Gerrit-Change-Number: 25657
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen
Gerrit-MessageType: newchange
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