[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.
Nils Asmussen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25649 )
Change subject: arch-riscv: show names of MiscRegs on accesses.
..
arch-riscv: show names of MiscRegs on accesses.
Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.
Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/riscv/isa.cc
1 file changed, 131 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a71733b..3f1a7e1 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -47,6 +47,133 @@
namespace RiscvISA
{
+const std::array MiscRegNames = {{
+[MISCREG_PRV] = "PRV",
+[MISCREG_ISA] = "ISA",
+[MISCREG_VENDORID] = "VENDORID",
+[MISCREG_ARCHID]= "ARCHID",
+[MISCREG_IMPID] = "IMPID",
+[MISCREG_HARTID]= "HARTID",
+[MISCREG_STATUS]= "STATUS",
+[MISCREG_IP]= "IP",
+[MISCREG_IE]= "IE",
+[MISCREG_CYCLE] = "CYCLE",
+[MISCREG_TIME] = "TIME",
+[MISCREG_INSTRET] = "INSTRET",
+[MISCREG_HPMCOUNTER03] = "HPMCOUNTER03",
+[MISCREG_HPMCOUNTER04] = "HPMCOUNTER04",
+[MISCREG_HPMCOUNTER05] = "HPMCOUNTER05",
+[MISCREG_HPMCOUNTER06] = "HPMCOUNTER06",
+[MISCREG_HPMCOUNTER07] = "HPMCOUNTER07",
+[MISCREG_HPMCOUNTER08] = "HPMCOUNTER08",
+[MISCREG_HPMCOUNTER09] = "HPMCOUNTER09",
+[MISCREG_HPMCOUNTER10] = "HPMCOUNTER10",
+[MISCREG_HPMCOUNTER11] = "HPMCOUNTER11",
+[MISCREG_HPMCOUNTER12] = "HPMCOUNTER12",
+[MISCREG_HPMCOUNTER13] = "HPMCOUNTER13",
+[MISCREG_HPMCOUNTER14] = "HPMCOUNTER14",
+[MISCREG_HPMCOUNTER15] = "HPMCOUNTER15",
+[MISCREG_HPMCOUNTER16] = "HPMCOUNTER16",
+[MISCREG_HPMCOUNTER17] = "HPMCOUNTER17",
+[MISCREG_HPMCOUNTER18] = "HPMCOUNTER18",
+[MISCREG_HPMCOUNTER19] = "HPMCOUNTER19",
+[MISCREG_HPMCOUNTER20] = "HPMCOUNTER20",
+[MISCREG_HPMCOUNTER21] = "HPMCOUNTER21",
+[MISCREG_HPMCOUNTER22] = "HPMCOUNTER22",
+[MISCREG_HPMCOUNTER23] = "HPMCOUNTER23",
+[MISCREG_HPMCOUNTER24] = "HPMCOUNTER24",
+[MISCREG_HPMCOUNTER25] = "HPMCOUNTER25",
+[MISCREG_HPMCOUNTER26] = "HPMCOUNTER26",
+[MISCREG_HPMCOUNTER27] = "HPMCOUNTER27",
+[MISCREG_HPMCOUNTER28] = "HPMCOUNTER28",
+[MISCREG_HPMCOUNTER29] = "HPMCOUNTER29",
+[MISCREG_HPMCOUNTER30] = "HPMCOUNTER30",
+[MISCREG_HPMCOUNTER31] = "HPMCOUNTER31",
+[MISCREG_HPMEVENT03]= "HPMEVENT03",
+[MISCREG_HPMEVENT04]= "HPMEVENT04",
+[MISCREG_HPMEVENT05]= "HPMEVENT05",
+[MISCREG_HPMEVENT06]= "HPMEVENT06",
+[MISCREG_HPMEVENT07]= "HPMEVENT07",
+[MISCREG_HPMEVENT08]= "HPMEVENT08",
+[MISCREG_HPMEVENT09]= "HPMEVENT09",
+[MISCREG_HPMEVENT10]= "HPMEVENT10",
+[MISCREG_HPMEVENT11]= "HPMEVENT11",
+[MISCREG_HPMEVENT12]= "HPMEVENT12",
+[MISCREG_HPMEVENT13]= "HPMEVENT13",
+[MISCREG_HPMEVENT14]= "HPMEVENT14",
+[MISCREG_HPMEVENT15]= "HPMEVENT15",
+[MISCREG_HPMEVENT16]= "HPMEVENT16",
+[MISCREG_HPMEVENT17]= "HPMEVENT17",
+[MISCREG_HPMEVENT18]= "HPMEVENT18",
+[MISCREG_HPMEVENT19]= "HPMEVENT19",
+[MISCREG_HPMEVENT20]= "HPMEVENT20",
+[MISCREG_HPMEVENT21]= "HPMEVENT21",
+[MISCREG_HPMEVENT22]= "HPMEVENT22",
+[MISCREG_HPMEVENT23]= "HPMEVENT23",
+[MISCREG_HPMEVENT24]= "HPMEVENT24",
+[MISCREG_HPMEVENT25]= "HPMEVENT25",
+[MISCREG_HPMEVENT26]= "HPMEVENT26",
+[MISCREG_HPMEVENT27]= "HPMEVENT27",
+[MISCREG_HPMEVENT28]= "HPMEVENT28",
+[MISCREG_HPMEVENT29]= "HPMEVENT29",
+[MISCREG_HPMEVENT30]= "HPMEVENT30",
+[MISCREG_HPMEVENT31]= "HPMEVENT31",
+[MISCREG_TSELECT] = "TSELECT",
+[MISCREG_TDATA1]= "TDATA1",
+[MISCREG_TDATA2]= "TDATA2",
+[MISCREG_TDATA3]= "TDATA3",
+[MISCREG_DCSR] = "DCSR",
+[MISCREG_DPC] = "DPC",
+[MISCREG_DSCRATCH] = "DSCRATCH",
+
+[MISCREG_MEDELEG] = "MEDELEG",
+[MISCREG_MIDELEG] = "MIDELEG",
+[MISCREG_MTVEC] = "MTVEC",
+[MISCREG_MCOUNTEREN]= "MCOUNTEREN",
+[MISCREG_MSCRATCH] = "MSCRATCH",
+[MISCREG_MEPC] = "MEPC",
+[MISCREG_MCAUSE]= "MCAUSE",
+[MISCREG_MTVAL] = "MTVAL",
+[MISCREG_PMPCFG0] = "PMPCFG0",
+// pmpcfg1 rv32 only
+[MISCREG_PMPCFG2] = "PMPCFG2",
+// pmpcfg3 rv32 only
+[MISCREG_PMPADDR00] = "P
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25649 )
Change subject: arch-riscv: show names of MiscRegs on accesses.
..
arch-riscv: show names of MiscRegs on accesses.
Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.
Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
---
M src/arch/riscv/isa.cc
1 file changed, 136 insertions(+), 3 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 861b19c..ba03f34 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -47,8 +47,140 @@
namespace RiscvISA
{
+const char *MiscRegNames[] = {
+"PRV",
+"ISA",
+"VENDORID",
+"ARCHID",
+"IMPID",
+"HARTID",
+"STATUS",
+"IP",
+"IE",
+"CYCLE",
+"TIME",
+"INSTRET",
+"HPMCOUNTER03",
+"HPMCOUNTER04",
+"HPMCOUNTER05",
+"HPMCOUNTER06",
+"HPMCOUNTER07",
+"HPMCOUNTER08",
+"HPMCOUNTER09",
+"HPMCOUNTER10",
+"HPMCOUNTER11",
+"HPMCOUNTER12",
+"HPMCOUNTER13",
+"HPMCOUNTER14",
+"HPMCOUNTER15",
+"HPMCOUNTER16",
+"HPMCOUNTER17",
+"HPMCOUNTER18",
+"HPMCOUNTER19",
+"HPMCOUNTER20",
+"HPMCOUNTER21",
+"HPMCOUNTER22",
+"HPMCOUNTER23",
+"HPMCOUNTER24",
+"HPMCOUNTER25",
+"HPMCOUNTER26",
+"HPMCOUNTER27",
+"HPMCOUNTER28",
+"HPMCOUNTER29",
+"HPMCOUNTER30",
+"HPMCOUNTER31",
+"HPMEVENT03",
+"HPMEVENT04",
+"HPMEVENT05",
+"HPMEVENT06",
+"HPMEVENT07",
+"HPMEVENT08",
+"HPMEVENT09",
+"HPMEVENT10",
+"HPMEVENT11",
+"HPMEVENT12",
+"HPMEVENT13",
+"HPMEVENT14",
+"HPMEVENT15",
+"HPMEVENT16",
+"HPMEVENT17",
+"HPMEVENT18",
+"HPMEVENT19",
+"HPMEVENT20",
+"HPMEVENT21",
+"HPMEVENT22",
+"HPMEVENT23",
+"HPMEVENT24",
+"HPMEVENT25",
+"HPMEVENT26",
+"HPMEVENT27",
+"HPMEVENT28",
+"HPMEVENT29",
+"HPMEVENT30",
+"HPMEVENT31",
+"TSELECT",
+"TDATA1",
+"TDATA2",
+"TDATA3",
+"DCSR",
+"DPC",
+"DSCRATCH",
+
+"MEDELEG",
+"MIDELEG",
+"MTVEC",
+"MCOUNTEREN",
+"MSCRATCH",
+"MEPC",
+"MCAUSE",
+"MTVAL",
+"PMPCFG0",
+// pmpcfg1 rv32 only
+"PMPCFG2",
+// pmpcfg3 rv32 only
+"PMPADDR00",
+"PMPADDR01",
+"PMPADDR02",
+"PMPADDR03",
+"PMPADDR04",
+"PMPADDR05",
+"PMPADDR06",
+"PMPADDR07",
+"PMPADDR08",
+"PMPADDR09",
+"PMPADDR10",
+"PMPADDR11",
+"PMPADDR12",
+"PMPADDR13",
+"PMPADDR14",
+"PMPADDR15",
+
+"SEDELEG",
+"SIDELEG",
+"STVEC",
+"SCOUNTEREN",
+"SSCRATCH",
+"SEPC",
+"SCAUSE",
+"STVAL",
+"SATP",
+
+"UTVEC",
+"USCRATCH",
+"UEPC",
+"UCAUSE",
+"UTVAL",
+"FFLAGS",
+"FRM",
+};
+
ISA::ISA(Params *p) : BaseISA(p)
{
+static_assert(
+sizeof(MiscRegNames) / sizeof(MiscRegNames[0]) == NumMiscRegs,
+"MiscRegNames not in sync with NumMiscRegs"
+);
+
miscRegFile.resize(NumMiscRegs);
clear();
}
@@ -105,8 +237,8 @@
panic("Illegal CSR index %#x\n", misc_reg);
return -1;
}
-DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg,
-miscRegFile[misc_reg]);
+DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#llx.\n",
+MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
return miscRegFile[misc_reg];
}
@@ -180,7 +312,8 @@
// Illegal CSR
panic("Illegal CSR index %#x\n", misc_reg);
}
-DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val);
+DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
+MiscRegNames[misc_reg], misc_reg, val);
miscRegFile[misc_reg] = val;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Gerrit-Change-Number: 25649
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen
Gerrit-MessageType: newchange
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