[gem5-dev] Change in gem5/gem5[develop]: base, arch-hsail: Fix GPU build

2020-04-03 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27136 )


Change subject: base,arch-hsail: Fix GPU build
..

base,arch-hsail: Fix GPU build

The GPU build is currently broken due to recent changes. This fixes
the build after changes to local access, removal of getSyscallArg,
and creating of AMO header in base.

Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27136
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Bradford Beckmann 
Maintainer: Anthony Gutierrez 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

---
M src/base/amo.hh
M src/gpu-compute/cl_driver.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
5 files changed, 17 insertions(+), 17 deletions(-)

Approvals:
  Bradford Beckmann: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/base/amo.hh b/src/base/amo.hh
index 718b346..44dec8b 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 

 struct AtomicOpFunctor
 {
diff --git a/src/gpu-compute/cl_driver.cc b/src/gpu-compute/cl_driver.cc
index d8a4618..ee86017 100644
--- a/src/gpu-compute/cl_driver.cc
+++ b/src/gpu-compute/cl_driver.cc
@@ -105,9 +105,6 @@
 int
 ClDriver::ioctl(ThreadContext *tc, unsigned req, Addr buf_addr)
 {
-int index = 2;
-auto process = tc->getProcessPtr();
-
 switch (req) {
   case HSA_GET_SIZES:
 {
diff --git a/src/gpu-compute/gpu_dyn_inst.hh  
b/src/gpu-compute/gpu_dyn_inst.hh

index a4a6ffb..bee08e3 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -251,31 +251,31 @@
 // when true, call execContinuation when response arrives
 bool useContinuation;

-template AtomicOpFunctor*
+template AtomicOpFunctorPtr
 makeAtomicOpFunctor(c0 *reg0, c0 *reg1)
 {
 if (isAtomicAnd()) {
-return new AtomicOpAnd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicOr()) {
-return new AtomicOpOr(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicXor()) {
-return new AtomicOpXor(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicCAS()) {
-return new AtomicOpCAS(*reg0, *reg1, cu);
+return m5::make_unique>(*reg0, *reg1, cu);
 } else if (isAtomicExch()) {
-return new AtomicOpExch(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicAdd()) {
-return new AtomicOpAdd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicSub()) {
-return new AtomicOpSub(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicInc()) {
-return new AtomicOpInc();
+return m5::make_unique>();
 } else if (isAtomicDec()) {
-return new AtomicOpDec();
+return m5::make_unique>();
 } else if (isAtomicMax()) {
-return new AtomicOpMax(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicMin()) {
-return new AtomicOpMin(*reg0);
+return m5::make_unique>(*reg0);
 } else {
 fatal("Unrecognized atomic operation");
 }
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 12fb9aa..2ae40da 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -43,6 +43,7 @@
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/regs/misc.hh"
+#include "arch/x86/regs/msr.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
@@ -426,7 +427,7 @@
 // If this is true, we're dealing with a request
 // to a non-memory address space.
 if (seg == SEGMENT_REG_MS) {
-return translateInt(mode == Read, req, tc);
+return translateInt(mode == Mode::Read, req, tc);
 }

 delayedResponse = false;
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 6ed4ba1..dbd3a16 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -175,7 +175,8 @@
  */
 std::vector entryList;

-Fault translateInt(const RequestPtr , ThreadContext *tc);
+Fault translateInt(bool read, const RequestPtr ,
+   ThreadContext *tc);

 Fault translate(const RequestPtr , ThreadContext *tc,
 Translation *translation, Mode mode, bool ,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27136
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[gem5-dev] Change in gem5/gem5[develop]: base, arch-hsail: Fix GPU build

2020-03-26 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27136 )



Change subject: base,arch-hsail: Fix GPU build
..

base,arch-hsail: Fix GPU build

The GPU build is currently broken due to recent changes. This fixes
the build after changes to local access, removal of getSyscallArg,
and creating of AMO header in base.

Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
---
M src/base/amo.hh
M src/gpu-compute/cl_driver.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
5 files changed, 17 insertions(+), 17 deletions(-)



diff --git a/src/base/amo.hh b/src/base/amo.hh
index 718b346..44dec8b 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 

 struct AtomicOpFunctor
 {
diff --git a/src/gpu-compute/cl_driver.cc b/src/gpu-compute/cl_driver.cc
index d8a4618..ee86017 100644
--- a/src/gpu-compute/cl_driver.cc
+++ b/src/gpu-compute/cl_driver.cc
@@ -105,9 +105,6 @@
 int
 ClDriver::ioctl(ThreadContext *tc, unsigned req, Addr buf_addr)
 {
-int index = 2;
-auto process = tc->getProcessPtr();
-
 switch (req) {
   case HSA_GET_SIZES:
 {
diff --git a/src/gpu-compute/gpu_dyn_inst.hh  
b/src/gpu-compute/gpu_dyn_inst.hh

index a4a6ffb..bee08e3 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -251,31 +251,31 @@
 // when true, call execContinuation when response arrives
 bool useContinuation;

-template AtomicOpFunctor*
+template AtomicOpFunctorPtr
 makeAtomicOpFunctor(c0 *reg0, c0 *reg1)
 {
 if (isAtomicAnd()) {
-return new AtomicOpAnd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicOr()) {
-return new AtomicOpOr(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicXor()) {
-return new AtomicOpXor(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicCAS()) {
-return new AtomicOpCAS(*reg0, *reg1, cu);
+return m5::make_unique>(*reg0, *reg1, cu);
 } else if (isAtomicExch()) {
-return new AtomicOpExch(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicAdd()) {
-return new AtomicOpAdd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicSub()) {
-return new AtomicOpSub(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicInc()) {
-return new AtomicOpInc();
+return m5::make_unique>();
 } else if (isAtomicDec()) {
-return new AtomicOpDec();
+return m5::make_unique>();
 } else if (isAtomicMax()) {
-return new AtomicOpMax(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicMin()) {
-return new AtomicOpMin(*reg0);
+return m5::make_unique>(*reg0);
 } else {
 fatal("Unrecognized atomic operation");
 }
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 12fb9aa..2ae40da 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -43,6 +43,7 @@
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/regs/misc.hh"
+#include "arch/x86/regs/msr.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
@@ -426,7 +427,7 @@
 // If this is true, we're dealing with a request
 // to a non-memory address space.
 if (seg == SEGMENT_REG_MS) {
-return translateInt(mode == Read, req, tc);
+return translateInt(mode == Mode::Read, req, tc);
 }

 delayedResponse = false;
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 6ed4ba1..dbd3a16 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -175,7 +175,8 @@
  */
 std::vector entryList;

-Fault translateInt(const RequestPtr , ThreadContext *tc);
+Fault translateInt(bool read, const RequestPtr ,
+   ThreadContext *tc);

 Fault translate(const RequestPtr , ThreadContext *tc,
 Translation *translation, Mode mode, bool ,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27136
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
Gerrit-Change-Number: 27136
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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