[gem5-dev] Change in gem5/gem5[develop]: cpu,mem,sim: Use ADD_STAT macro where possible
Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38916 )
Change subject: cpu,mem,sim: Use ADD_STAT macro where possible
..
cpu,mem,sim: Use ADD_STAT macro where possible
Change-Id: I3cf0a2a321742445cf7100115eacbc411c70f4fb
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38916
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/base.cc
M src/mem/abstract_mem.cc
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/multi.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/sector_tags.cc
M src/mem/coherent_xbar.cc
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
M src/mem/xbar.cc
M src/sim/root.cc
M src/sim/workload.hh
16 files changed, 148 insertions(+), 189 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index af928f1..793fc64 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -732,12 +732,10 @@
BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
: ::Stats::Group(parent),
-simInsts(this, "sim_insts", "Number of instructions simulated"),
-simOps(this, "sim_ops", "Number of ops (including micro ops)
simulated"),
-hostInstRate(this, "host_inst_rate",
- "Simulator instruction rate (inst/s)"),
-hostOpRate(this, "host_op_rate",
- "Simulator op (including micro ops) rate (op/s)")
+ADD_STAT(simInsts, "Number of instructions simulated"),
+ADD_STAT(simOps, "Number of ops (including micro ops) simulated"),
+ADD_STAT(hostInstRate, "Simulator instruction rate (inst/s)"),
+ADD_STAT(hostOpRate, "Simulator op (including micro ops) rate (op/s)")
{
simInsts
.functor(BaseCPU::numSimulatedInsts)
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index c8853d1..e7c460c 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -111,26 +111,19 @@
AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
: Stats::Group(&_mem), mem(_mem),
-bytesRead(this, "bytes_read",
- "Number of bytes read from this memory"),
-bytesInstRead(this, "bytes_inst_read",
- "Number of instructions bytes read from this memory"),
-bytesWritten(this, "bytes_written",
- "Number of bytes written to this memory"),
-numReads(this, "num_reads",
- "Number of read requests responded to by this memory"),
-numWrites(this, "num_writes",
- "Number of write requests responded to by this memory"),
-numOther(this, "num_other",
- "Number of other requests responded to by this memory"),
-bwRead(this, "bw_read",
- "Total read bandwidth from this memory (bytes/s)"),
-bwInstRead(this, "bw_inst_read",
- "Instruction read bandwidth from this memory (bytes/s)"),
-bwWrite(this, "bw_write",
-"Write bandwidth from this memory (bytes/s)"),
-bwTotal(this, "bw_total",
-"Total bandwidth to/from this memory (bytes/s)")
+ADD_STAT(bytesRead, "Number of bytes read from this memory"),
+ADD_STAT(bytesInstRead,
+ "Number of instructions bytes read from this memory"),
+ADD_STAT(bytesWritten, "Number of bytes written to this memory"),
+ADD_STAT(numReads, "Number of read requests responded to by this
memory"),
+ADD_STAT(numWrites,
+ "Number of write requests responded to by this memory"),
+ADD_STAT(numOther, "Number of other requests responded to by this
memory"),
+ADD_STAT(bwRead, "Total read bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwInstRead,
+ "Instruction read bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwWrite, "Write bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwTotal, "Total bandwidth to/from this memory (bytes/s)")
{
}
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index d28a34e..023d0a9 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2104,67 +2104,44 @@
BaseCache::CacheStats::CacheStats(BaseCache &c)
: Stats::Group(&c), cache(c),
-demandHits(this, "demand_hits", "number of demand (read+write) hits"),
-
-overallHits(this, "overall_hits", "number of overall hits"),
-demandMisses(this, "demand_misses",
- "number of demand (read+write) misses"),
-overallMisses(this, "overall_misses", "number of overall misses"),
-demandMissLatency(this, "demand_miss_latency",
- "number
[gem5-dev] Change in gem5/gem5[develop]: cpu,mem,sim: Use ADD_STAT macro where possible
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38916 )
Change subject: cpu,mem,sim: Use ADD_STAT macro where possible
..
cpu,mem,sim: Use ADD_STAT macro where possible
Change-Id: I3cf0a2a321742445cf7100115eacbc411c70f4fb
Signed-off-by: Hoa Nguyen
---
M src/cpu/base.cc
M src/mem/abstract_mem.cc
M src/mem/cache/base.cc
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/multi.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/sector_tags.cc
M src/mem/coherent_xbar.cc
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/xbar.cc
M src/sim/root.cc
M src/sim/workload.hh
13 files changed, 101 insertions(+), 150 deletions(-)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 0c998be..f933774 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -734,12 +734,10 @@
BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
: ::Stats::Group(parent),
-simInsts(this, "sim_insts", "Number of instructions simulated"),
-simOps(this, "sim_ops", "Number of ops (including micro ops)
simulated"),
-hostInstRate(this, "host_inst_rate",
- "Simulator instruction rate (inst/s)"),
-hostOpRate(this, "host_op_rate",
- "Simulator op (including micro ops) rate (op/s)")
+ADD_STAT(simInsts, "Number of instructions simulated"),
+ADD_STAT(simOps, "Number of ops (including micro ops) simulated"),
+ADD_STAT(hostInstRate, "Simulator instruction rate (inst/s)"),
+ADD_STAT(hostOpRate, "Simulator op (including micro ops) rate (op/s)")
{
simInsts
.functor(BaseCPU::numSimulatedInsts)
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 7e09832..782a298 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -113,26 +113,19 @@
AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
: Stats::Group(&_mem), mem(_mem),
-bytesRead(this, "bytes_read",
- "Number of bytes read from this memory"),
-bytesInstRead(this, "bytes_inst_read",
- "Number of instructions bytes read from this memory"),
-bytesWritten(this, "bytes_written",
- "Number of bytes written to this memory"),
-numReads(this, "num_reads",
- "Number of read requests responded to by this memory"),
-numWrites(this, "num_writes",
- "Number of write requests responded to by this memory"),
-numOther(this, "num_other",
- "Number of other requests responded to by this memory"),
-bwRead(this, "bw_read",
- "Total read bandwidth from this memory (bytes/s)"),
-bwInstRead(this, "bw_inst_read",
- "Instruction read bandwidth from this memory (bytes/s)"),
-bwWrite(this, "bw_write",
-"Write bandwidth from this memory (bytes/s)"),
-bwTotal(this, "bw_total",
-"Total bandwidth to/from this memory (bytes/s)")
+ADD_STAT(bytesRead, "Number of bytes read from this memory"),
+ADD_STAT(bytesInstRead,
+ "Number of instructions bytes read from this memory"),
+ADD_STAT(bytesWritten, "Number of bytes written to this memory"),
+ADD_STAT(numReads, "Number of read requests responded to by this
memory"),
+ADD_STAT(numWrites,
+ "Number of write requests responded to by this memory"),
+ADD_STAT(numOther, "Number of other requests responded to by this
memory"),
+ADD_STAT(bwRead, "Total read bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwInstRead,
+ "Instruction read bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwWrite, "Write bandwidth from this memory (bytes/s)"),
+ADD_STAT(bwTotal, "Total bandwidth to/from this memory (bytes/s)")
{
}
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 3181a0c..efdb548 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2106,67 +2106,44 @@
BaseCache::CacheStats::CacheStats(BaseCache &c)
: Stats::Group(&c), cache(c),
-demandHits(this, "demand_hits", "number of demand (read+write) hits"),
-
-overallHits(this, "overall_hits", "number of overall hits"),
-demandMisses(this, "demand_misses",
- "number of demand (read+write) misses"),
-overallMisses(this, "overall_misses", "number of overall misses"),
-demandMissLatency(this, "demand_miss_latency",
- "number of demand (read+write) miss cycles"),
-overallMissLatency(this, "overall_miss_latency",
- "number of overall miss cycles"),
-demandAccesses(this, "demand_accesses",
- "number of demand (read+write) accesses"),
-overallAccesses(this, "overall_accesses",
-"number of overall (read+write) accesses"),
-demandMissRate(this, "demand_miss_rate",
- "miss rate for demand accesses
