[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HTM CPU API
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30322 ) Change subject: cpu: Add HTM CPU API .. cpu: Add HTM CPU API JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: Iff95eb97603b4cb9629c04382a824b02594ee5c7 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30322 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/simple/atomic.hh M src/cpu/simple/base.hh M src/cpu/simple/timing.cc M src/cpu/simple/timing.hh 6 files changed, 62 insertions(+), 4 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 562a332..613ffd1 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited + * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019-2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -1827,5 +1827,13 @@ } } +template +void +FullO3CPU::htmSendAbortSignal(ThreadID tid, uint64_t htmUid, + HtmFailureFaultCause cause) +{ +panic("not yet supported!"); +} + // Forward declaration of FullO3CPU. template class FullO3CPU; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index cc0e2cd..137fbc8 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013, 2016-2019 ARM Limited + * Copyright (c) 2011-2013, 2016-2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -788,6 +788,11 @@ //number of misc Stats::Scalar miscRegfileReads; Stats::Scalar miscRegfileWrites; + + public: +// hardware transactional memory +void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, +HtmFailureFaultCause cause); }; #endif // __CPU_O3_CPU_HH__ diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 7333e1f..2d0a465 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2015, 2018 ARM Limited + * Copyright (c) 2012-2013, 2015, 2018, 2020 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -219,6 +219,18 @@ const std::vector& byte_enable = std::vector()) override; +Fault initiateHtmCmd(Request::Flags flags) override +{ +panic("initiateHtmCmd() is for timing accesses, and should " + "never be called on AtomicSimpleCPU.\n"); +} + +void htmSendAbortSignal(HtmFailureFaultCause cause) override +{ +panic("htmSendAbortSignal() is for timing accesses, and should " + "never be called on AtomicSimpleCPU.\n"); +} + Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector& byte_enable = std::vector()) diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 9f5bf66..82f52d9 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -176,6 +176,21 @@ void serializeThread(CheckpointOut , ThreadID tid) const override; void unserializeThread(CheckpointIn , ThreadID tid) override; +/** Hardware transactional memory commands (HtmCmds), e.g. start a + * transaction and commit a transaction, are memory operations but are + * neither really (true) loads nor stores. For this reason the interface + * is extended and initiateHtmCmd() is used to instigate the command. */ +virtual Fault initiateHtmCmd(Request::Flags flags) = 0; + +/** This function is used to instruct the memory subsystem that a + * transaction should be aborted and the speculative state should be + * thrown away. This is called in the transaction's very last breath in + * the core. Afterwards, the core throws away its speculative state and + * resumes execution at the point the transaction started, i.e. reverses + * time. When instruction execution resumes, the core expects the + * memory subsystem to be in a stable, i.e. pre-speculative, state as + * well. */ +virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0; }; #endif // __CPU_SIMPLE_BASE_HH__ diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 84d7d0e..d3adbcc 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1055,6 +1055,19 @@ dcachePort.printAddr(a); } +Fault +TimingSimpleCPU::initiateHtmCmd(Request::Flags flags) +{ +panic("not yet supported!"); +return NoFault; +} + +void +TimingSimpleCPU::htmSendAbortSignal(HtmFailureFaultCause cause) +{ +panic("not yet
[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HTM CPU API
Hello Timothy Hayes, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/30322 to review the following change. Change subject: cpu: Add HTM CPU API .. cpu: Add HTM CPU API JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: Iff95eb97603b4cb9629c04382a824b02594ee5c7 Signed-off-by: Giacomo Travaglini --- M src/cpu/checker/cpu.hh M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/simple/atomic.hh M src/cpu/simple/base.hh M src/cpu/simple/timing.cc M src/cpu/simple/timing.hh 7 files changed, 68 insertions(+), 4 deletions(-) diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6bd7022..24fad1c 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -434,6 +434,12 @@ thread->setMemAccPredicate(val); } +Fault initiateHtmCmd(Request::Flags flags) override +{ +panic("not yet supported!"); +return NoFault; +} + TheISA::PCState pcState() const override { return thread->pcState(); } void pcState(const TheISA::PCState ) override diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index b3faf31..79fd1d7 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1833,5 +1833,13 @@ } } +template +void +FullO3CPU::htmSendAbortSignal(ThreadID tid, uint64_t htmUid, + HtmFailureFaultCause cause) +{ +panic("not yet supported!"); +} + // Forward declaration of FullO3CPU. template class FullO3CPU; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index c3d911b..61bbdbd 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -788,6 +788,11 @@ //number of misc Stats::Scalar miscRegfileReads; Stats::Scalar miscRegfileWrites; + + public: +// hardware transactional memory +void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, +HtmFailureFaultCause cause); }; #endif // __CPU_O3_CPU_HH__ diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 53fe0fc..e35cfaa 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2015, 2018 ARM Limited + * Copyright (c) 2012-2013, 2015, 2018-2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -219,6 +219,18 @@ const std::vector& byte_enable = std::vector()) override; +Fault initiateHtmCmd(Request::Flags flags) override +{ +panic("initiateHtmCmd() is for timing accesses, and should " + "never be called on AtomicSimpleCPU.\n"); +} + +void htmSendAbortSignal(HtmFailureFaultCause cause) override +{ +panic("htmSendAbortSignal() is for timing accesses, and should " + "never be called on AtomicSimpleCPU.\n"); +} + Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector& byte_enable = std::vector()) diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 323850a..b69765b 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012,2015,2018 ARM Limited + * Copyright (c) 2011-2012,2015,2018-2019 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -168,6 +168,21 @@ void serializeThread(CheckpointOut , ThreadID tid) const override; void unserializeThread(CheckpointIn , ThreadID tid) override; +/** Hardware transactional memory commands (HtmCmds), e.g. start a + * transaction and commit a transaction, are memory operations but are + * neither really (true) loads nor stores. For this reason the interface + * is extended and initiateHtmCmd() is used to instigate the command. */ +virtual Fault initiateHtmCmd(Request::Flags flags) = 0; + +/** This function is used to instruct the memory subsystem that a + * transaction should be aborted and the speculative state should be + * thrown away. This is called in the transaction's very last breath in + * the core. Afterwards, the core throws away its speculative state and + * resumes execution at the point the transaction started, i.e. reverses + * time. When instruction execution resumes, the core expects the + * memory subsystem to be in a stable, i.e. pre-speculative, state as + * well. */ +virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0; }; #endif // __CPU_SIMPLE_BASE_HH__ diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index c1c70cb..a509562 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1,6 +1,6 @@ /* * Copyright 2014 Google, Inc. - * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited + * Copyright (c) 2010-2013,2015,2017-2019 ARM Limited * All rights reserved * * The license