Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/26203 )
Change subject: cpu-o3: Fix unset scoreboard in vector mode switching
..
cpu-o3: Fix unset scoreboard in vector mode switching
This is another fix for the AArch32-AArch64 interprocessing issue
introduced in
3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model.
Register mapping between AArch32 and AArch64 is explicitly defined in
ARMv8 manual. This allows software to read registers right after a state
switch without writing them first, and it is indeed common for software
to save registers to memory first before using them.
In gem5's implementation of vector mode switching, however, vectors may
not be marked as ready right after a state switch. Software reads toward
vectors at this time will stall O3CPU forever. This patch fixes this by
marking all mapped vectors (or vector elements, depending on AArch32 or
AArch64) as ready right after switching vector mode.
Change-Id: I609552c543dad8da66939c0a3079d73d48e92163
Signed-off-by: Hsuan Hsu
Signed-off-by: Howard Wang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26203
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
2 files changed, 29 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e2c7270..5f0a98b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -846,6 +846,28 @@
template
void
+FullO3CPU::setVectorsAsReady(ThreadID tid)
+{
+if (vecMode == Enums::Elem) {
+for (auto v = 0; v < TheISA::NumVecRegs; v++)
+for (auto e = 0; e < TheISA::NumVecElemPerVecReg; e++)
+scoreboard.setReg(
+commitRenameMap[tid].lookup(
+RegId(VecElemClass, v, e)
+)
+);
+} else if (vecMode == Enums::Full) {
+for (auto v = 0; v < TheISA::NumVecRegs; v++)
+scoreboard.setReg(
+commitRenameMap[tid].lookup(
+RegId(VecRegClass, v)
+)
+);
+}
+}
+
+template
+void
FullO3CPU::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
{
auto pc = this->pcState(tid);
@@ -860,6 +882,7 @@
renameMap[tid].switchMode(vecMode);
commitRenameMap[tid].switchMode(vecMode);
renameMap[tid].switchFreeList(freelist);
+setVectorsAsReady(tid);
}
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 01f58df..c3d911b 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -313,6 +313,12 @@
/** Traps to handle given fault. */
void trap(const Fault , ThreadID tid, const StaticInstPtr );
+/**
+ * Mark vector fields in scoreboard as ready right after switching
+ * vector mode, since software may read vectors at this time.
+ */
+void setVectorsAsReady(ThreadID tid);
+
/** Check if a change in renaming is needed for vector registers.
* The vecMode variable is updated and propagated to rename maps.
*
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/26203
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I609552c543dad8da66939c0a3079d73d48e92163
Gerrit-Change-Number: 26203
Gerrit-PatchSet: 3
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
