[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: MemDepUnit tracks load-acquire/store-release
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27132 )
Change subject: cpu-o3: MemDepUnit tracks load-acquire/store-release
..
cpu-o3: MemDepUnit tracks load-acquire/store-release
MemDepUnit tracks loads/stores that are also barriers, which is the case
of load-acquire / store-release instructions. The tracking logic is also
extended to consider multiple outstanding barriers.
Change-Id: I95b0c710d7c7e4a138492177e3eaaf5143e9a0ba
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27132
Reviewed-by: Daniel Carvalho
Reviewed-by: Anthony Gutierrez
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
2 files changed, 103 insertions(+), 85 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index c4a3310..3d24b1f 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2014 ARM Limited
+ * Copyright (c) 2012, 2014, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
#include
#include
#include
+#include
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
@@ -177,7 +178,7 @@
public:
/** Constructs a memory dependence entry. */
MemDepEntry(const DynInstPtr _inst)
-: inst(new_inst), regsReady(false), memDepReady(false),
+: inst(new_inst), regsReady(false), memDeps(0),
completed(false), squashed(false)
{
#ifdef DEBUG
@@ -216,8 +217,8 @@
/** If the registers are ready or not. */
bool regsReady;
-/** If all memory dependencies have been satisfied. */
-bool memDepReady;
+/** Number of memory dependencies that need to be satisfied. */
+int memDeps;
/** If the instruction is completed. */
bool completed;
/** If the instruction is squashed. */
@@ -257,14 +258,20 @@
*/
MemDepPred depPred;
+/** Sequence numbers of outstanding load barriers. */
+std::unordered_set loadBarrierSNs;
+
+/** Sequence numbers of outstanding store barriers. */
+std::unordered_set storeBarrierSNs;
+
/** Is there an outstanding load barrier that loads must wait on. */
-bool loadBarrier;
-/** The sequence number of the load barrier. */
-InstSeqNum loadBarrierSN;
+bool hasLoadBarrier() const { return !loadBarrierSNs.empty(); }
+
/** Is there an outstanding store barrier that loads must wait on. */
-bool storeBarrier;
-/** The sequence number of the store barrier. */
-InstSeqNum storeBarrierSN;
+bool hasStoreBarrier() const { return !storeBarrierSNs.empty(); }
+
+/** Inserts the SN of a barrier inst. to the list of tracked barriers
*/
+void insertBarrierSN(const DynInstPtr _inst);
/** Pointer to the IQ. */
InstructionQueue *iqPtr;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index c712965..9a50341 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2014 ARM Limited
+ * Copyright (c) 2012, 2014, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
#include
+#include
#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/mem_dep_unit.hh"
@@ -50,8 +51,7 @@
template
MemDepUnit::MemDepUnit()
-: loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
- storeBarrierSN(0), iqPtr(NULL)
+: iqPtr(NULL)
{
}
@@ -60,8 +60,7 @@
: _name(params->name + ".memdepunit"),
depPred(params->store_set_clear_period, params->SSITSize,
params->LFSTSize),
- loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
- storeBarrierSN(0), iqPtr(NULL)
+ iqPtr(NULL)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
}
@@ -155,8 +154,8 @@
MemDepUnit::takeOverFrom()
{
// Be sure to reset all state.
-loadBarrier = storeBarrier = false;
-loadBarrierSN = storeBarrierSN = 0;
+loadBarrierSNs.clear();
+storeBarrierSNs.clear();
depPred.clear();
}
@@ -169,6 +168,29 @@
template
void
+MemDepUnit::insertBarrierSN(const DynInstPtr _inst)
+{
+InstSeqNum barr_sn = barr_inst->seqNum;
+// Memory barriers block loads and stores, write barriers only stores.
+if (barr_inst->isMemBarrier()) {
+loadBarrierSNs.insert(barr_sn);
+storeBarrierSNs.insert(barr_sn);
+DPRINTF(MemDepUnit, "Inserted a memory
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: MemDepUnit tracks load-acquire/store-release
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27132 )
Change subject: cpu-o3: MemDepUnit tracks load-acquire/store-release
..
cpu-o3: MemDepUnit tracks load-acquire/store-release
MemDepUnit tracks loads/stores that are also barriers, which is the case
of load-acquire / store-release instructions. The tracking logic is also
extended to consider multiple outstanding barriers.
Change-Id: I95b0c710d7c7e4a138492177e3eaaf5143e9a0ba
Signed-off-by: Tiago Mück
---
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
2 files changed, 118 insertions(+), 73 deletions(-)
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index c4a3310..54d2363 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2014 ARM Limited
+ * Copyright (c) 2012, 2014, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
#include
#include
#include
+#include
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
@@ -177,7 +178,7 @@
public:
/** Constructs a memory dependence entry. */
MemDepEntry(const DynInstPtr _inst)
-: inst(new_inst), regsReady(false), memDepReady(false),
+: inst(new_inst), regsReady(false), memDeps(0),
completed(false), squashed(false)
{
#ifdef DEBUG
@@ -216,8 +217,8 @@
/** If the registers are ready or not. */
bool regsReady;
-/** If all memory dependencies have been satisfied. */
-bool memDepReady;
+/** Number of memory dependencies that need to be satisfied. */
+int memDeps;
/** If the instruction is completed. */
bool completed;
/** If the instruction is squashed. */
@@ -257,14 +258,22 @@
*/
MemDepPred depPred;
+/** Sequence numbers of outstanding load barriers. */
+std::unordered_set loadBarrierSNs;
+
+/** Sequence numbers of outstanding store barriers. */
+std::unordered_set storeBarrierSNs;
+
/** Is there an outstanding load barrier that loads must wait on. */
-bool loadBarrier;
-/** The sequence number of the load barrier. */
-InstSeqNum loadBarrierSN;
+bool loadBarrier() { return loadBarrierSNs.size() != 0; }
+
/** Is there an outstanding store barrier that loads must wait on. */
-bool storeBarrier;
-/** The sequence number of the store barrier. */
-InstSeqNum storeBarrierSN;
+bool storeBarrier() { return storeBarrierSNs.size() != 0; }
+
+void _insertBarrier(const DynInstPtr _inst);
+
+void _completeBarrier(const DynInstPtr );
+
/** Pointer to the IQ. */
InstructionQueue *iqPtr;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index c712965..6fa1607 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2014 ARM Limited
+ * Copyright (c) 2012, 2014, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
#include
+#include
#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/mem_dep_unit.hh"
@@ -50,8 +51,7 @@
template
MemDepUnit::MemDepUnit()
-: loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
- storeBarrierSN(0), iqPtr(NULL)
+: iqPtr(NULL)
{
}
@@ -60,8 +60,7 @@
: _name(params->name + ".memdepunit"),
depPred(params->store_set_clear_period, params->SSITSize,
params->LFSTSize),
- loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
- storeBarrierSN(0), iqPtr(NULL)
+ iqPtr(NULL)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
}
@@ -155,8 +154,8 @@
MemDepUnit::takeOverFrom()
{
// Be sure to reset all state.
-loadBarrier = storeBarrier = false;
-loadBarrierSN = storeBarrierSN = 0;
+loadBarrierSNs.clear();
+storeBarrierSNs.clear();
depPred.clear();
}
@@ -169,6 +168,48 @@
template
void
+MemDepUnit::_insertBarrier(const DynInstPtr _inst)
+{
+InstSeqNum barr_sn = barr_inst->seqNum;
+// Memory barriers block loads and stores, write barriers only stores.
+if (barr_inst->isMemBarrier()) {
+loadBarrierSNs.insert(barr_sn);
+storeBarrierSNs.insert(barr_sn);
+DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
+barr_inst->pcState(),barr_sn);
+} else if (barr_inst->isWriteBarrier()) {
+storeBarrierSNs.insert(barr_sn);
+DPRINTF(MemDepUnit, "Inserted a write barrier %s SN:%lli\n",
+barr_inst->pcState(),barr_sn);
+}
+if (loadBarrierSNs.size() || storeBarrierSNs.size())
+DPRINTF(MemDepUnit, "Outstanding load barriers =
