Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35699 )
Change subject: mem-cache: Isolate prefetching bit
..
mem-cache: Isolate prefetching bit
Previously the prefetching bit was among the status bits;
yet, it has no correlation with the other bits. It has
been isolated as a single boolean, with a respective getter
and setter.
Change-Id: Ibe76e1196ca17a7c9ab9bda2216186707427cb64
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35699
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/noncoherent_cache.cc
4 files changed, 17 insertions(+), 9 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index fc2115a..7b6b3c3 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -367,7 +367,7 @@
ppHit->notify(pkt);
if (prefetcher && blk && blk->wasPrefetched()) {
-blk->status &= ~BlkHWPrefetched;
+blk->clearPrefetched();
}
handleTimingReqHit(pkt, blk, request_time);
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 8e45ea3..9e87c2a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -850,7 +850,7 @@
case MSHR::Target::FromPrefetcher:
assert(tgt_pkt->cmd == MemCmd::HardPFReq);
if (blk)
-blk->status |= BlkHWPrefetched;
+blk->setPrefetched();
delete tgt_pkt;
break;
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index b0d45af..4483fb1 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -69,8 +69,6 @@
BlkReadable = 0x04,
/** dirty (modified) */
BlkDirty = 0x08,
-/** block was a hardware prefetch yet unaccessed*/
-BlkHWPrefetched = 0x20,
/** block holds compressed data */
BlkCompressed = 0x80
};
@@ -176,6 +174,7 @@
virtual void invalidate()
{
TaggedEntry::invalidate();
+clearPrefetched();
setTaskId(ContextSwitchTaskId::Unknown);
status = 0;
whenReady = MaxTick;
@@ -198,10 +197,16 @@
* be touched.
* @return True if the block was a hardware prefetch, unaccesed.
*/
-bool wasPrefetched() const
-{
-return (status & BlkHWPrefetched) != 0;
-}
+bool wasPrefetched() const { return _prefetched; }
+
+/**
+ * Clear the prefetching bit. Either because it was recently used, or
due
+ * to the block being invalidated.
+ */
+void clearPrefetched() { _prefetched = false; }
+
+/** Marks this blocks as a recently prefetched block. */
+void setPrefetched() { _prefetched = false; }
/**
* Get tick at which block's data will be available for access.
@@ -423,6 +428,9 @@
* meaningful if the block is valid.
*/
Tick _tickInserted;
+
+/** Whether this block is an unaccessed hardware prefetch. */
+bool _prefetched;
};
/**
diff --git a/src/mem/cache/noncoherent_cache.cc
b/src/mem/cache/noncoherent_cache.cc
index 5ca1da0..0cea494 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -288,7 +288,7 @@
assert(tgt_pkt->cmd == MemCmd::HardPFReq);
if (blk)
-blk->status |= BlkHWPrefetched;
+blk->setPrefetched();
// We have filled the block and the prefetcher does not
// require responses.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibe76e1196ca17a7c9ab9bda2216186707427cb64
Gerrit-Change-Number: 35699
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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