[gem5-dev] Change in gem5/gem5[develop]: misc: Remove sim/cur_tick dependency from sim/core.hh
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43592 )
Change subject: misc: Remove sim/cur_tick dependency from sim/core.hh
..
misc: Remove sim/cur_tick dependency from sim/core.hh
Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.
Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M ext/sst/gem5.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/linux/fs_workload.hh
M src/arch/arm/semihosting.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/riscv/isa.cc
M src/arch/x86/regs/int.hh
M src/base/pollevent.cc
M src/base/pollevent.hh
M src/base/stats/storage.hh
M src/base/trace.hh
M src/base/vnc/vncserver.cc
M src/cpu/inst_pb_trace.cc
M src/cpu/o3/cpu.cc
M src/cpu/pc_event.cc
M src/cpu/testers/traffic_gen/trace_gen.cc
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/dev/intel_8254_timer.cc
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_iface.cc
M src/dev/net/dist_iface.hh
M src/dev/net/etherbus.cc
M src/dev/net/etherdump.cc
M src/dev/net/etherlink.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/tcp_iface.cc
M src/dev/pci/device.cc
M src/dev/storage/ide_disk.cc
M src/dev/virtio/fs9p.cc
M src/kern/freebsd/events.cc
M src/mem/cache/base.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/queue.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/write_queue_entry.hh
M src/mem/comm_monitor.cc
M src/mem/mem_checker.cc
M src/mem/mem_checker.hh
M src/mem/packet.hh
M src/mem/probes/mem_trace.cc
M src/mem/request.hh
M src/mem/ruby/profiler/StoreTrace.cc
M src/mem/ruby/structures/BankedArray.cc
M src/mem/ruby/structures/BankedArray.hh
M src/python/pybind11/core.cc
M src/sim/core.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/global_event.cc
M src/sim/init.cc
M src/sim/init_signals.cc
M src/sim/power_state.cc
M src/sim/power_state.hh
M src/sim/root.cc
M src/sim/stat_control.hh
M src/systemc/channel/sc_clock.cc
M src/systemc/core/event.cc
M src/systemc/core/sc_main.cc
M src/systemc/core/scheduler.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/utils/tracefile.cc
M src/systemc/utils/vcd.cc
M util/systemc/gem5_within_systemc/sc_module.cc
72 files changed, 52 insertions(+), 54 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index efe73eb..3049567 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -52,7 +52,7 @@
#include
// gem5 Headers
-#include
+#include
#include
#include
#include
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 5f7562e..e9b468d 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -31,7 +31,6 @@
#include "arch/arm/regs/misc.hh"
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
-#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 1ab1b29..4f14e7e 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -30,7 +30,6 @@
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
-#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
namespace gem5
diff --git a/src/arch/arm/linux/fs_workload.hh
b/src/arch/arm/linux/fs_workload.hh
index 3531ea9..659de9d 100644
--- a/src/arch/arm/linux/fs_workload.hh
+++ b/src/arch/arm/linux/fs_workload.hh
@@ -52,7 +52,6 @@
#include "base/output.hh"
#include "kern/linux/events.hh"
#include "params/ArmFsLinux.hh"
-#include "sim/core.hh"
namespace gem5
{
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 2c237ca..a21852d 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -49,6 +49,7 @@
#include "arch/arm/utility.hh"
#include "cpu/thread_context.hh"
#include "mem/port_proxy.hh"
+#include "sim/core.hh"
#include "sim/guest_abi.hh"
#include "sim/sim_object.hh"
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index 52b9558..f262c6c 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++
[gem5-dev] Change in gem5/gem5[develop]: misc: Remove sim/cur_tick dependency from sim/core.hh
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43592 )
Change subject: misc: Remove sim/cur_tick dependency from sim/core.hh
..
misc: Remove sim/cur_tick dependency from sim/core.hh
Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.
Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho
---
M ext/sst/gem5.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/linux/fs_workload.hh
M src/arch/arm/semihosting.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/riscv/isa.cc
M src/arch/x86/regs/int.hh
M src/base/pollevent.cc
M src/base/pollevent.hh
M src/base/stats/storage.hh
M src/base/trace.hh
M src/base/vnc/vncserver.cc
M src/cpu/inst_pb_trace.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/pc_event.cc
M src/cpu/static_inst.cc
M src/cpu/testers/traffic_gen/trace_gen.cc
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/dev/intel_8254_timer.cc
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_iface.cc
M src/dev/net/dist_iface.hh
M src/dev/net/etherbus.cc
M src/dev/net/etherdump.cc
M src/dev/net/etherlink.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/tcp_iface.cc
M src/dev/pci/device.cc
M src/dev/storage/ide_disk.cc
M src/dev/virtio/fs9p.cc
M src/kern/freebsd/events.cc
M src/mem/cache/base.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/queue.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/write_queue_entry.hh
M src/mem/comm_monitor.cc
M src/mem/mem_checker.cc
M src/mem/mem_checker.hh
M src/mem/packet.hh
M src/mem/probes/mem_trace.cc
M src/mem/request.hh
M src/mem/ruby/profiler/StoreTrace.cc
M src/mem/ruby/structures/BankedArray.cc
M src/mem/ruby/structures/BankedArray.hh
M src/python/pybind11/core.cc
M src/sim/core.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/global_event.cc
M src/sim/init.cc
M src/sim/init_signals.cc
M src/sim/power_state.cc
M src/sim/power_state.hh
M src/sim/root.cc
M src/sim/stat_control.hh
M src/systemc/channel/sc_clock.cc
M src/systemc/core/event.cc
M src/systemc/core/sc_main.cc
M src/systemc/core/scheduler.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/utils/tracefile.cc
M src/systemc/utils/vcd.cc
M src/unittest/stattest.cc
M util/systemc/gem5_within_systemc/sc_module.cc
M util/tlm/examples/common/report_handler.cc
77 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index 3d48e93..b0a111e 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -52,7 +52,7 @@
#include
// gem5 Headers
-#include
+#include
#include
#include
#include
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 72ce17e..f59e1ab 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -30,7 +30,6 @@
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
-#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
namespace FastModel
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 98184f9..05cbcda 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -30,7 +30,6 @@
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
-#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
namespace FastModel
diff --git a/src/arch/arm/linux/fs_workload.hh
b/src/arch/arm/linux/fs_workload.hh
index 03fb6c1..568d33e 100644
--- a/src/arch/arm/linux/fs_workload.hh
+++ b/src/arch/arm/linux/fs_workload.hh
@@ -52,7 +52,6 @@
#include "base/output.hh"
#include "kern/linux/events.hh"
#include "params/ArmFsLinux.hh"
-#include "sim/core.hh"
namespace ArmISA
{
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 991b65b..f0bb971 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -49,6 +49,7 @@
#include "arch/arm/utility.hh"
#include "cpu/thread_context.hh"
#include "mem/port_proxy.hh"
+#include "sim/core.hh"
#include "sim/guest_abi.hh"
#include "sim/sim_object.hh"
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index db9c7e1..fbae4c2 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -50,7 +50,7 @@
#include "cpu/thread_context.hh"
