[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

2018-06-14 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10602 )


Change subject: arch-arm: Read APSR in User Mode
..

arch-arm: Read APSR in User Mode

This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.

Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10602
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/miscregs.hh
2 files changed, 12 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index f1c6acf..ef579bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -226,7 +226,7 @@
 cpsr.c = CondCodesC;
 cpsr.v = CondCodesV;
 cpsr.ge = CondCodesGE;
-Dest = cpsr & 0xF8FF03DF
+Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
 '''

 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b00e5ff..f9386b4 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1423,6 +1423,17 @@
 static const uint32_t CondCodesMask   = 0xF00F;
 static const uint32_t CpsrMaskQ   = 0x0800;

+// APSR (Application Program Status Register Mask). It is the user  
level

+// alias for the CPSR. The APSR is a subset of the CPSR. Although
+// bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
+// APSR:
+// Bit[9] returns the value of CPSR.E.
+// Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
+static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask |  
0x01D0;

+
+// CPSR (Current Program Status Register Mask).
+static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
+
 BitUnion32(HDCR)
 Bitfield<11>   tdra;
 Bitfield<10>   tdosa;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Gerrit-Change-Number: 10602
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

2018-05-30 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10602

to review the following change.


Change subject: arch-arm: Read APSR in User Mode
..

arch-arm: Read APSR in User Mode

This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.

Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/miscregs.hh
2 files changed, 12 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index f1c6acf..ef579bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -226,7 +226,7 @@
 cpsr.c = CondCodesC;
 cpsr.v = CondCodesV;
 cpsr.ge = CondCodesGE;
-Dest = cpsr & 0xF8FF03DF
+Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
 '''

 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b00e5ff..f9386b4 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1423,6 +1423,17 @@
 static const uint32_t CondCodesMask   = 0xF00F;
 static const uint32_t CpsrMaskQ   = 0x0800;

+// APSR (Application Program Status Register Mask). It is the user  
level

+// alias for the CPSR. The APSR is a subset of the CPSR. Although
+// bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
+// APSR:
+// Bit[9] returns the value of CPSR.E.
+// Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
+static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask |  
0x01D0;

+
+// CPSR (Current Program Status Register Mask).
+static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
+
 BitUnion32(HDCR)
 Bitfield<11>   tdra;
 Bitfield<10>   tdosa;

--
To view, visit https://gem5-review.googlesource.com/10602
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Gerrit-Change-Number: 10602
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
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