[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Hit latencies defined by the controllers
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18413 )
Change subject: mem-ruby: Hit latencies defined by the controllers
..
mem-ruby: Hit latencies defined by the controllers
Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.
Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro
Reviewed-by: Nikos Nikoleris
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M configs/ruby/GPU_RfO.py
M configs/ruby/MOESI_AMD_Base.py
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.py
10 files changed, 34 insertions(+), 47 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index c9bda0b..1f4df38 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -115,8 +115,6 @@
self.L2cache.create(options)
self.sequencer = RubySequencer()
-self.sequencer.icache_hit_latency = 2
-self.sequencer.dcache_hit_latency = 2
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
@@ -128,12 +126,13 @@
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
-self.sequencer1.icache_hit_latency = 2
-self.sequencer1.dcache_hit_latency = 2
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
self.sequencer1.is_cpu_sequencer = True
+# Defines icache/dcache hit latency
+self.mandatory_queue_latency = 2
+
self.issue_latency = options.cpu_to_dir_latency
self.send_evictions = send_evicts(options)
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 5c4bbe0..a1faf1d 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -102,8 +102,6 @@
self.L2cache.create(options)
self.sequencer = RubySequencer()
-self.sequencer.icache_hit_latency = 2
-self.sequencer.dcache_hit_latency = 2
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
@@ -115,12 +113,13 @@
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
-self.sequencer1.icache_hit_latency = 2
-self.sequencer1.dcache_hit_latency = 2
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
self.sequencer1.is_cpu_sequencer = True
+# Defines icache/dcache hit latency
+self.mandatory_queue_latency = 2
+
self.issue_latency = options.cpu_to_dir_latency
self.send_evictions = send_evicts(options)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 68edcba..c953e82 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -55,6 +55,7 @@
m_number_of_TBEs(p->number_of_TBEs),
m_transitions_per_cycle(p->transitions_per_cycle),
m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
+ m_mandatory_queue_latency(p->mandatory_queue_latency),
memoryPort(csprintf("%s.memory", name()), this, ""),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
{
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 4d06546..bd0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,201
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Hit latencies defined by the controllers
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18413
Change subject: mem-ruby: Hit latencies defined by the controllers
..
mem-ruby: Hit latencies defined by the controllers
Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.
Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck
---
M configs/ruby/GPU_RfO.py
M configs/ruby/MOESI_AMD_Base.py
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.py
10 files changed, 34 insertions(+), 47 deletions(-)
diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index c9bda0b..1f4df38 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -115,8 +115,6 @@
self.L2cache.create(options)
self.sequencer = RubySequencer()
-self.sequencer.icache_hit_latency = 2
-self.sequencer.dcache_hit_latency = 2
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
@@ -128,12 +126,13 @@
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
-self.sequencer1.icache_hit_latency = 2
-self.sequencer1.dcache_hit_latency = 2
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
self.sequencer1.is_cpu_sequencer = True
+# Defines icache/dcache hit latency
+self.mandatory_queue_latency = 2
+
self.issue_latency = options.cpu_to_dir_latency
self.send_evictions = send_evicts(options)
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index d465083..cfa7449 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -102,8 +102,6 @@
self.L2cache.create(options)
self.sequencer = RubySequencer()
-self.sequencer.icache_hit_latency = 2
-self.sequencer.dcache_hit_latency = 2
self.sequencer.version = self.seqCount()
self.sequencer.icache = self.L1Icache
self.sequencer.dcache = self.L1D0cache
@@ -115,12 +113,13 @@
self.sequencer1.version = self.seqCount()
self.sequencer1.icache = self.L1Icache
self.sequencer1.dcache = self.L1D1cache
-self.sequencer1.icache_hit_latency = 2
-self.sequencer1.dcache_hit_latency = 2
self.sequencer1.ruby_system = ruby_system
self.sequencer1.coreid = 1
self.sequencer1.is_cpu_sequencer = True
+# Defines icache/dcache hit latency
+self.mandatory_queue_latency = 2
+
self.issue_latency = options.cpu_to_dir_latency
self.send_evictions = send_evicts(options)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index fa1c936..a665062 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -55,6 +55,7 @@
m_number_of_TBEs(p->number_of_TBEs),
m_transitions_per_cycle(p->transitions_per_cycle),
m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
+ m_mandatory_queue_latency(p->mandatory_queue_latency),
memoryPort(csprintf("%s.memory", name()), this, ""),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
{
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 5e39a28..5e0fa28 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -102,6 +102,13 @@
virtual Sequencer* getCPUSequencer() const = 0;
virtual GPUCoalescer* getGPUCoalescer() const = 0;
+// This latency is used by the sequencer when enqueueing requests.
+// Different latencies may
