Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34417 )
Change subject: mem-ruby: Update port names in Ruby
......................................................................
mem-ruby: Update port names in Ruby
After the terminology update commit there were still many confusing
names in the Ruby ports. This changeset is a proposal for updating these
names.
For an example use case, see the following resources changeset.
https://gem5-review.googlesource.com/c/public/gem5-resources/+/34416
Change-Id: I01d4f24a70b300e39438ee147dfab7a8d674d5c7
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34417
Reviewed-by: Ayaz Akram <yazak...@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbr...@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/Sequencer.py
3 files changed, 23 insertions(+), 12 deletions(-)
Approvals:
Ayaz Akram: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/Controller.py
b/src/mem/ruby/slicc_interface/Controller.py
index 2c6c655..1f9c0db 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -66,5 +66,8 @@
Param.Cycles(1, "Default latency for requests added to the " \
"mandatory queue on top-level controllers")
- memory = RequestPort("Port for attaching a memory controller")
+ memory_out_port = RequestPort("Port for attaching a memory controller")
+ memory = DeprecatedParam(memory_out_port, "The request port for Ruby "
+ "memory output to the main memory is now called `memory_out_port`")
+
system = Param.System(Parent.any, "system object parameter")
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 4fc41c9..fc011cc 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -61,13 +61,13 @@
memResponsePort(csprintf("%s-mem-response-port", name()), this,
p->ruby_system->getAccessBackingStore(), -1,
p->no_retry_on_stall),
- gotAddrRanges(p->port_request_ports_connection_count),
+ gotAddrRanges(p->port_interrupt_out_port_connection_count),
m_isCPUSequencer(p->is_cpu_sequencer)
{
assert(m_version != -1);
// create the response ports based on the number of connected ports
- for (size_t i = 0; i < p->port_response_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p->port_in_ports_connection_count; ++i) {
response_ports.push_back(new MemResponsePort(csprintf
("%s.response_ports%d", name(), i), this,
p->ruby_system->getAccessBackingStore(),
@@ -75,7 +75,7 @@
}
// create the request ports based on the number of connected ports
- for (size_t i = 0; i < p->port_request_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p->port_interrupt_out_port_connection_count;
++i) {
request_ports.push_back(new PioRequestPort(csprintf(
"%s.request_ports%d", name(), i), this));
}
@@ -99,7 +99,7 @@
return memResponsePort;
} else if (if_name == "pio_response_port") {
return pioResponsePort;
- } else if (if_name == "request_ports") {
+ } else if (if_name == "interrupt_out_port") {
// used by the x86 CPUs to connect the interrupt PIO and interrupt
// response port
if (idx >= static_cast<PortID>(request_ports.size())) {
@@ -107,7 +107,7 @@
}
return *request_ports[idx];
- } else if (if_name == "response_ports") {
+ } else if (if_name == "in_ports") {
// used by the CPUs to connect the caches to the interconnect, and
// for the x86 case also the interrupt request port
if (idx >= static_cast<PortID>(response_ports.size())) {
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 6869fc2..0a28d36 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -35,18 +35,26 @@
cxx_header = "mem/ruby/system/RubyPort.hh"
version = Param.Int(0, "")
- response_ports = VectorResponsePort("CPU response port")
- slave = DeprecatedParam(response_ports,
- '`slave` is now called `response_ports`')
- request_ports = VectorRequestPort("CPU request port")
- master = DeprecatedParam(request_ports,
- '`master` is now called `request_ports`')
+ in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
+ "The CPU request ports should be connected to this. If a
CPU "
+ "has multiple ports (e.g., I/D ports) all of the ports for
a "
+ "single CPU can connect to one RubyPort.")
+ slave = DeprecatedParam(in_ports,
+ '`slave` is now called `in_port`')
+
+ interrupt_out_port = VectorRequestPort("Port to connect to x86
interrupt "
+ "controller to send the CPU requests from
outside.")
+ master = DeprecatedParam(interrupt_out_port,
+ '`master` is now called `interrupt_out_port`')
+
pio_request_port = RequestPort("Ruby pio request port")
pio_master_port = DeprecatedParam(pio_request_port,
'`pio_master_port` is now called
`pio_request_port`')
+
mem_request_port = RequestPort("Ruby mem request port")
mem_master_port = DeprecatedParam(mem_request_port,
'`mem_master_port` is now called
`mem_request_port`')
+
pio_response_port = ResponsePort("Ruby pio response port")
pio_slave_port = DeprecatedParam(pio_response_port,
'`pio_slave_port` is now called
`pio_response_port`')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I01d4f24a70b300e39438ee147dfab7a8d674d5c7
Gerrit-Change-Number: 34417
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Bradford Beckmann <bradford.beckm...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: Timothy Hayes <timothy.ha...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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