[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MCR/MRC disassemble

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5862 )


Change subject: arch-arm: Fix MCR/MRC disassemble
..

arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc.cc
1 file changed, 2 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f..ec1b935 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@
 {
 std::stringstream ss;
 printMnemonic(ss);
-printIntReg(ss, dest);
+printMiscReg(ss, dest);
 ss << ", ";
 printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
 return ss.str();
 }

@@ -273,8 +272,7 @@
 printMnemonic(ss);
 printIntReg(ss, dest);
 ss << ", ";
-printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
+printMiscReg(ss, op1);
 return ss.str();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Gerrit-Change-Number: 5862
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MCR/MRC disassemble

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5862

to review the following change.


Change subject: arch-arm: Fix MCR/MRC disassemble
..

arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/misc.cc
1 file changed, 2 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f..ec1b935 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@
 {
 std::stringstream ss;
 printMnemonic(ss);
-printIntReg(ss, dest);
+printMiscReg(ss, dest);
 ss << ", ";
 printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
 return ss.str();
 }

@@ -273,8 +272,7 @@
 printMnemonic(ss);
 printIntReg(ss, dest);
 ss << ", ";
-printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
+printMiscReg(ss, op1);
 return ss.str();
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Gerrit-Change-Number: 5862
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
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