[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MSR/MRS disassemble

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5861 )


Change subject: arch-arm: Fix MSR/MRS disassemble
..

arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/templates/misc64.isa
5 files changed, 132 insertions(+), 13 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 465bafa..b40de02 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@

 std::string
 RegRegRegImmOp64::generateDisassembly(
-Addr pc, const SymbolTable *symtab) const
+Addr pc, const SymbolTable *symtab) const
 {
 std::stringstream ss;
 printMnemonic(ss, "", false);
@@ -71,3 +71,27 @@
 {
 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
 }
+
+std::string
+MiscRegRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printMiscReg(ss, dest);
+ss << ", ";
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegMiscRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printIntReg(ss, dest);
+ss << ", ";
+printMiscReg(ss, op1);
+return ss.str();
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e182..384d946 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@
 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

 };

+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+MiscRegIndex dest;
+IntRegIndex op1;
+uint32_t imm;
+
+MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, MiscRegIndex _dest,
+  IntRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+IntRegIndex dest;
+MiscRegIndex op1;
+uint32_t imm;
+
+RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, IntRegIndex _dest,
+  MiscRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2c33e24..d640caf 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,12 +369,13 @@
 return new Dczva(machInst, rt, (IntRegIndex)  
miscReg, iss);


 if (read) {
-StaticInstPtr si = new Mrs64(machInst, rt,  
(IntRegIndex) miscReg, iss);
+StaticInstPtr si = new Mrs64(machInst, rt,  
miscReg, iss);

 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
 si->setFlag(StaticInst::IsUnverifiable);
 return si;
-} else
-return new Msr64(machInst, (IntRegIndex)  
miscReg, rt, iss);

+} else {
+return new Msr64(machInst, miscReg, rt, iss);
+}
 } else 

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MSR/MRS disassemble

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5861

to review the following change.


Change subject: arch-arm: Fix MSR/MRS disassemble
..

arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/templates/misc64.isa
5 files changed, 132 insertions(+), 13 deletions(-)



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 465bafa..b40de02 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@

 std::string
 RegRegRegImmOp64::generateDisassembly(
-Addr pc, const SymbolTable *symtab) const
+Addr pc, const SymbolTable *symtab) const
 {
 std::stringstream ss;
 printMnemonic(ss, "", false);
@@ -71,3 +71,27 @@
 {
 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
 }
+
+std::string
+MiscRegRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printMiscReg(ss, dest);
+ss << ", ";
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegMiscRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printIntReg(ss, dest);
+ss << ", ";
+printMiscReg(ss, op1);
+return ss.str();
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e182..384d946 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@
 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

 };

+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+MiscRegIndex dest;
+IntRegIndex op1;
+uint32_t imm;
+
+MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, MiscRegIndex _dest,
+  IntRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+IntRegIndex dest;
+MiscRegIndex op1;
+uint32_t imm;
+
+RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, IntRegIndex _dest,
+  MiscRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2c33e24..d640caf 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,12 +369,13 @@
 return new Dczva(machInst, rt, (IntRegIndex)  
miscReg, iss);


 if (read) {
-StaticInstPtr si = new Mrs64(machInst, rt,  
(IntRegIndex) miscReg, iss);
+StaticInstPtr si = new Mrs64(machInst, rt,  
miscReg, iss);

 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
 si->setFlag(StaticInst::IsUnverifiable);
 return si;
-} else
-return new Msr64(machInst, (IntRegIndex)  
miscReg, rt, iss);

+} else {
+return new Msr64(machInst, miscReg, rt, iss);
+}
 } else if  
(miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {

 std::string full_mnem = csprintf("%s %s",
 read ? "mrs" : "msr", miscRegName[miscReg]);
diff --git a/src/arch/arm/isa/insts/data64.isa  
b/src/arch/arm/isa/insts/data64.isa

index d0ee439..887130f 100644
---