subject:"\[gem5\-dev\] Change in public\/gem5\[master\]\: arm\: Enable ns registers access in secure mode"

[gem5-dev] Change in public/gem5[master]: arm: Enable ns registers access in secure mode

2017-12-01 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6201 )


Change subject: arm: Enable ns registers access in secure mode
..

arm: Enable ns registers access in secure mode

Arm security extension introduced register banking between secure and
non-secure mode. This has been removed in armv8 using AArch64 in EL3,
where the decoded register is by default the non-secure version. Using
non-secure register infos(flags) was preventing secure execution to
access the register with the MRC/MCR at EL1.
The patch updates the following banked registers' flags so that their
non-secure version can be accessed in secure mode:

MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0,
MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR,
MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1,
MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL,
MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL

For those registers the following permission bits have been set:

MISCREG_PRI_S_RD
MISCREG_PRI_S_WR

Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Giacomo Gabrielli 
Reviewed-on: https://gem5-review.googlesource.com/6201
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 28 insertions(+), 28 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d31c84c..d08f751 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -344,7 +344,7 @@
 // MISCREG_CSSELR
 bitset(string("00010001")),
 // MISCREG_CSSELR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_CSSELR_S
 bitset(string("001100110011")),
 // MISCREG_VPIDR
@@ -354,13 +354,13 @@
 // MISCREG_SCTLR
 bitset(string("00010001")),
 // MISCREG_SCTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_SCTLR_S
 bitset(string("001100110011")),
 // MISCREG_ACTLR
 bitset(string("00010001")),
 // MISCREG_ACTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_ACTLR_S
 bitset(string("001100110011")),
 // MISCREG_CPACR
@@ -388,19 +388,19 @@
 // MISCREG_TTBR0
 bitset(string("00010001")),
 // MISCREG_TTBR0_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR0_S
 bitset(string("001100110011")),
 // MISCREG_TTBR1
 bitset(string("00010001")),
 // MISCREG_TTBR1_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR1_S
 bitset(string("001100110011")),
 // MISCREG_TTBCR
 bitset(string("00010001")),
 // MISCREG_TTBCR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBCR_S
 bitset(string("001100110011")),
 // MISCREG_HTCR
@@ -410,31 +410,31 @@
 // MISCREG_DACR
 bitset(string("00010001")),
 // MISCREG_DACR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DACR_S
 bitset(string("001100110011")),
 // MISCREG_DFSR
 bitset(string("00010001")),
 // MISCREG_DFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DFSR_S
 bitset(string("001100110011")),
 // MISCREG_IFSR
 bitset(string("00010001")),
 // MISCREG_IFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_IFSR_S
 bitset(string("001100110011")),
 // MISCREG_ADFSR
 bitset(string("00010100")),
 // MISCREG_ADFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_ADFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_AIFSR
 bitset(string("00010100")),
 // MISCREG_AIFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_AIFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_HADFSR
@@ -446,13 +446,13 @@
 // MISCREG_DFAR
 bitset(string("00010001")),
 // MISCREG_DFAR_NS
-

[gem5-dev] Change in public/gem5[master]: arm: Enable ns registers access in secure mode

2017-11-30 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/6201



Change subject: arm: Enable ns registers access in secure mode
..

arm: Enable ns registers access in secure mode

Arm security extension introduced register banking between secure and
non-secure mode. This has been removed in armv8 using AArch64 in EL3,
where the decoded register is by default the non-secure version. Using
non-secure register infos(flags) was preventing secure execution to
access the register with the MRC/MCR at EL1.
The patch updates the following banked registers' flags so that their
non-secure version can be accessed in secure mode:

MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0,
MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR,
MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1,
MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL,
MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL

For those registers the following permission bits have been set:

MISCREG_PRI_S_RD
MISCREG_PRI_S_WR

Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Giacomo Gabrielli 
---
M src/arch/arm/miscregs.cc
1 file changed, 28 insertions(+), 28 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d31c84c..d08f751 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -344,7 +344,7 @@
 // MISCREG_CSSELR
 bitset(string("00010001")),
 // MISCREG_CSSELR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_CSSELR_S
 bitset(string("001100110011")),
 // MISCREG_VPIDR
@@ -354,13 +354,13 @@
 // MISCREG_SCTLR
 bitset(string("00010001")),
 // MISCREG_SCTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_SCTLR_S
 bitset(string("001100110011")),
 // MISCREG_ACTLR
 bitset(string("00010001")),
 // MISCREG_ACTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_ACTLR_S
 bitset(string("001100110011")),
 // MISCREG_CPACR
@@ -388,19 +388,19 @@
 // MISCREG_TTBR0
 bitset(string("00010001")),
 // MISCREG_TTBR0_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR0_S
 bitset(string("001100110011")),
 // MISCREG_TTBR1
 bitset(string("00010001")),
 // MISCREG_TTBR1_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR1_S
 bitset(string("001100110011")),
 // MISCREG_TTBCR
 bitset(string("00010001")),
 // MISCREG_TTBCR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBCR_S
 bitset(string("001100110011")),
 // MISCREG_HTCR
@@ -410,31 +410,31 @@
 // MISCREG_DACR
 bitset(string("00010001")),
 // MISCREG_DACR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DACR_S
 bitset(string("001100110011")),
 // MISCREG_DFSR
 bitset(string("00010001")),
 // MISCREG_DFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DFSR_S
 bitset(string("001100110011")),
 // MISCREG_IFSR
 bitset(string("00010001")),
 // MISCREG_IFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_IFSR_S
 bitset(string("001100110011")),
 // MISCREG_ADFSR
 bitset(string("00010100")),
 // MISCREG_ADFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_ADFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_AIFSR
 bitset(string("00010100")),
 // MISCREG_AIFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_AIFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_HADFSR
@@ -446,13 +446,13 @@
 // MISCREG_DFAR
 bitset(string("00010001")),
 // MISCREG_DFAR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DFAR_S
 bitset(string("001100110011")),
 // MISCREG_IFAR
 bitset(string("00010001")),
 // MISCREG_IFAR_NS
-

[gem5-dev] Change in public/gem5[master]: arm: Enable ns registers access in secure mode

[gem5-dev] Change in public/gem5[master]: arm: Enable ns registers access in secure mode

2 matches

Site Navigation

Mail list logo

Footer information