[gem5-dev] Re: Build failed in Jenkins: Nightly #118
The proposed patch fixes the issue. My long runs now pass again. On Wed, Nov 4, 2020 at 8:14 AM Jason Lowe-Power via gem5-dev < gem5-dev@gem5.org> wrote: > Hi all, > > I'm pretty sure https://gem5-review.googlesource.com/c/public/gem5/+/34984 > is the breaking change on last night's build. > > It's unfortunate how much time/effort supporting MIPS and other ISAs > takes... > > Cheers, > Jason > > On Tue, Nov 3, 2020 at 11:03 PM jenkins-no-reply--- via gem5-dev < > gem5-dev@gem5.org> wrote: > >> See < >> https://jenkins.gem5.org/job/Nightly/118/display/redirect?page=changes> >> >> Changes: >> >> [gabe.black] arch: Clean up the __init__s in (Sub)OperandList. >> >> [davide.basilio.bartolini] configs: Do not require default options for >> caches >> >> [giacomo.travaglini] cpu, fastmodel: Remove the old getDTBPtr/getITBPtr >> virtual methods >> >> [giacomo.travaglini] arch-arm: Add el2Enabled cached variable >> >> [giacomo.travaglini] arch-arm: Fix implementation of TLBI_VMALL >> instructions >> >> [giacomo.travaglini] arch-arm: TlbEntry flush to be considered as >> functional lookup >> >> [giacomo.travaglini] arch-arm: Do not use _flushMva for TLBI IPA >> >> [yuhsingw] configs: Add dtb-gen to fs_bigLITTLE.py >> >> >> -- >> [...truncated 68.77 KB...] >> [SO PARAM] DMA_Controller -> MIPS/params/DMA_Controller.hh >> [MAKE INC] MIPS/mem/ruby/common/BoolVec.hh -> protocol/BoolVec.hh >> [MAKE INC] MIPS/mem/ruby/structures/CacheMemory.hh -> >> protocol/CacheMemory.hh >> [MAKE INC] MIPS/mem/ruby/system/DMASequencer.hh -> >> protocol/DMASequencer.hh >> [MAKE INC] MIPS/mem/ruby/structures/DirectoryMemory.hh -> >> protocol/DirectoryMemory.hh >> [MAKE INC] MIPS/mem/ruby/system/HTMSequencer.hh -> >> protocol/HTMSequencer.hh >> [SO PARAM] RubyPrefetcher -> MIPS/params/RubyPrefetcher.hh >> [MAKE INC] MIPS/mem/ruby/structures/RubyPrefetcher.hh -> >> protocol/RubyPrefetcher.hh >> [MAKE INC] MIPS/mem/ruby/system/Sequencer.hh -> protocol/Sequencer.hh >> [MAKE INC] MIPS/mem/ruby/common/Set.hh -> protocol/Set.hh >> [MAKE INC] MIPS/mem/ruby/structures/TimerTable.hh -> >> protocol/TimerTable.hh >> [SO PARAM] RubyWireBuffer -> MIPS/params/RubyWireBuffer.hh >> [MAKE INC] MIPS/mem/ruby/structures/WireBuffer.hh -> >> protocol/WireBuffer.hh >> [MAKE INC] MIPS/mem/ruby/common/WriteMask.hh -> protocol/WriteMask.hh >> [MAKE INC] MIPS/mem/ruby/slicc_interface/AbstractCacheEntry.hh -> >> protocol/AbstractCacheEntry.hh >> [ CXX] MIPS/mem/ruby/protocol/DMA_Controller.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/DMA_Event.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/DMA_State.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/DMA_TBE.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/DMA_Transitions.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/DMA_Wakeup.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/DirectoryRequestType.cc -> .o >> [SO PARAM] Directory_Controller -> MIPS/params/Directory_Controller.hh >> [ CXX] MIPS/mem/ruby/protocol/Directory_Controller.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/Directory_Entry.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/Directory_Event.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/Directory_State.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/Directory_TBE.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/Directory_Transitions.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/Directory_Wakeup.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/HtmCallbackMode.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/HtmFailedInCacheReason.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/InvalidateGeneratorStatus.cc -> .o >> [SO PARAM] L1Cache_Controller -> MIPS/params/L1Cache_Controller.hh >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_Controller.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_Entry.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_Event.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_State.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_TBE.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_Transitions.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/L1Cache_Wakeup.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/LinkDirection.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/LockStatus.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MachineType.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MaskPredictorIndex.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MaskPredictorTraining.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MaskPredictorType.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MemoryControlRequestType.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MemoryMsg.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MemoryRequestType.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/MessageSizeType.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/PrefetchBit.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/RequestMsg.cc -> .o >> [ CXX] MIPS/mem/ruby/protocol/RequestStatus.cc -> .o >> [ CXX]
[gem5-dev] Re: Build failed in Jenkins: Nightly #118
Hi all, I'm pretty sure https://gem5-review.googlesource.com/c/public/gem5/+/34984 is the breaking change on last night's build. It's unfortunate how much time/effort supporting MIPS and other ISAs takes... Cheers, Jason On Tue, Nov 3, 2020 at 11:03 PM jenkins-no-reply--- via gem5-dev < gem5-dev@gem5.org> wrote: > See < > https://jenkins.gem5.org/job/Nightly/118/display/redirect?page=changes> > > Changes: > > [gabe.black] arch: Clean up the __init__s in (Sub)OperandList. > > [davide.basilio.bartolini] configs: Do not require default options for > caches > > [giacomo.travaglini] cpu, fastmodel: Remove the old getDTBPtr/getITBPtr > virtual methods > > [giacomo.travaglini] arch-arm: Add el2Enabled cached variable > > [giacomo.travaglini] arch-arm: Fix implementation of TLBI_VMALL > instructions > > [giacomo.travaglini] arch-arm: TlbEntry flush to be considered as > functional lookup > > [giacomo.travaglini] arch-arm: Do not use _flushMva for TLBI IPA > > [yuhsingw] configs: Add dtb-gen to fs_bigLITTLE.py > > > -- > [...truncated 68.77 KB...] > [SO PARAM] DMA_Controller -> MIPS/params/DMA_Controller.hh > [MAKE INC] MIPS/mem/ruby/common/BoolVec.hh -> protocol/BoolVec.hh > [MAKE INC] MIPS/mem/ruby/structures/CacheMemory.hh -> > protocol/CacheMemory.hh > [MAKE INC] MIPS/mem/ruby/system/DMASequencer.hh -> > protocol/DMASequencer.hh > [MAKE INC] MIPS/mem/ruby/structures/DirectoryMemory.hh -> > protocol/DirectoryMemory.hh > [MAKE INC] MIPS/mem/ruby/system/HTMSequencer.hh -> > protocol/HTMSequencer.hh > [SO PARAM] RubyPrefetcher -> MIPS/params/RubyPrefetcher.hh > [MAKE INC] MIPS/mem/ruby/structures/RubyPrefetcher.hh -> > protocol/RubyPrefetcher.hh > [MAKE INC] MIPS/mem/ruby/system/Sequencer.hh -> protocol/Sequencer.hh > [MAKE INC] MIPS/mem/ruby/common/Set.hh -> protocol/Set.hh > [MAKE INC] MIPS/mem/ruby/structures/TimerTable.hh -> > protocol/TimerTable.hh > [SO PARAM] RubyWireBuffer -> MIPS/params/RubyWireBuffer.hh > [MAKE INC] MIPS/mem/ruby/structures/WireBuffer.hh -> > protocol/WireBuffer.hh > [MAKE INC] MIPS/mem/ruby/common/WriteMask.hh -> protocol/WriteMask.hh > [MAKE INC] MIPS/mem/ruby/slicc_interface/AbstractCacheEntry.hh -> > protocol/AbstractCacheEntry.hh > [ CXX] MIPS/mem/ruby/protocol/DMA_Controller.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/DMA_Event.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/DMA_State.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/DMA_TBE.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/DMA_Transitions.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/DMA_Wakeup.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/DirectoryRequestType.cc -> .o > [SO PARAM] Directory_Controller -> MIPS/params/Directory_Controller.hh > [ CXX] MIPS/mem/ruby/protocol/Directory_Controller.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/Directory_Entry.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/Directory_Event.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/Directory_State.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/Directory_TBE.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/Directory_Transitions.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/Directory_Wakeup.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/HtmCallbackMode.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/HtmFailedInCacheReason.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/InvalidateGeneratorStatus.cc -> .o > [SO PARAM] L1Cache_Controller -> MIPS/params/L1Cache_Controller.hh > [ CXX] MIPS/mem/ruby/protocol/L1Cache_Controller.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/L1Cache_Entry.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/L1Cache_Event.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/L1Cache_State.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/L1Cache_TBE.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/L1Cache_Transitions.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/L1Cache_Wakeup.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/LinkDirection.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/LockStatus.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MachineType.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MaskPredictorIndex.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MaskPredictorTraining.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MaskPredictorType.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MemoryControlRequestType.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MemoryMsg.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MemoryRequestType.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/MessageSizeType.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/PrefetchBit.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/RequestMsg.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/RequestStatus.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/ResponseMsg.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/RubyAccessMode.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/RubyRequestType.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/SequencerMsg.cc -> .o > [ CXX] MIPS/mem/ruby/protocol/SequencerRequestType.cc -> .o > [
