On 26/08/2016 09:58, Bjoern A. Zeeb wrote:
On 25 Aug 2016, at 22:09, Andreas Hansson wrote:
Hi all,
Thanks a lot for that reply.
Two thoughts:
1. Does X86 + o3 + classic memory system actually work?
2. The interleaving of “real” timing accesses and the functional “debug”
accesses is not
On 25 Aug 2016, at 22:09, Andreas Hansson wrote:
Hi all,
Thanks a lot for that reply.
Two thoughts:
1. Does X86 + o3 + classic memory system actually work?
2. The interleaving of “real” timing accesses and the functional
“debug”
accesses is not well defined. In general I would encourage
>Brandon
>
>-Original Message-
>From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Bjoern A.
>Zeeb
>Sent: Monday, August 15, 2016 8:08 AM
>To: gem5 Developer List <gem5-dev@gem5.org>
>Subject: [gem5-dev] X86 RSP return address (after MemWrite) not ye
Developer List <gem5-dev@gem5.org>
Subject: [gem5-dev] X86 RSP return address (after MemWrite) not yet updated
issue?
Hi,
I was trying to skip FreeBSD’s DELAY() on X86_64 very much like we do on ARM
for Linux (or FreeBSD for that matter) and started to implement things and
found a s
Hi,
I was trying to skip FreeBSD’s DELAY() on X86_64 very much like we do
on ARM for Linux (or FreeBSD for that matter) and started to implement
things and found a strange behaviour:
From my src/arch/x86/utility.cc
void
skipFunction(ThreadContext *tc)
{
PCState newPC = tc->pcState();
