[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick

2010-09-03 Thread Cron Daemon
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. *

[m5-dev] error with gcc 4.1/gcc 4.2

2010-09-03 Thread biswabandan panda
hi , i am getting Info: Tree vectorizer in GCC 4.4.1 4.4.2 is buggy, disabling. can u tell me how to fix it.in ubuntu 9.01 ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] error with gcc 4.1/gcc 4.2

2010-09-03 Thread Ali Saidi
It's just a informative message that the tree vectorizer in the compiler is being disabled. If you really want it to be enabled (you probably wont notice a performance difference), you'll need to update your compiler. Ali On Fri, 3 Sep 2010 17:10:53 +0530, biswabandan panda wrote: hi , i

[m5-dev] performance analysis

2010-09-03 Thread biswabandan panda
hi all, i am totally new to m5,how to start with m5,i am able to run the examples in configs/exe but i want to know how to get the statistics for each cache let say in a 4 core system,having intel nehelam type memory model, and i want to play with it with different parameter changing

Re: [m5-dev] Cache Port Count Bug?

2010-09-03 Thread Yuval Peress
The additional returned access do appear to arrive from the L2 and are assigned to the port through the handleResponse function in mem/cache/cache_impl.hh. Specifically caused by the while(mshr-hasTargets()) look which puts multiple responses on the cpu side port. The port then sends them 1

Re: [m5-dev] Cache Port Count Bug?

2010-09-03 Thread Steve Reinhardt
On Fri, Sep 3, 2010 at 8:32 AM, Yuval Peress per...@cs.fsu.edu wrote: The additional returned access do appear to arrive from the L2 and are assigned to the port through the handleResponse function in mem/cache/cache_impl.hh. Specifically caused by the while(mshr-hasTargets()) look which puts