changeset 9e9db0c974e3 in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=9e9db0c974e3
description:
Ruby: Added figures for overview, data structures and timing for the
Memory Controller.
The data structure and timing diagrams were adapted/taken from a
presentation
changeset 3a5726a3e1da in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=3a5726a3e1da
description:
Ruby: Added FSM diagrams for MI_example cache coherence protocol.
diffstat:
ruby/figures/MI_example_cache_FSM.jpg |0
ruby/figures/MI_example_dir_FSM.jpg |0
changeset 01b8bcdb3a1c in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=01b8bcdb3a1c
description:
Ruby: Added FSM diagrams for MOESI_CMP_directory cache coherence
protocol.
diffstat:
ruby/figures/MOESI_CMP_directory_L1cache_FSM.jpg|0
changeset 7555e9135731 in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=7555e9135731
description:
Ruby: Added high-level figure for SLICC.
This was taken from the GEMS tutorial in ISCA 2005.
diffstat:
ruby/figures/slicc_overview.jpg |0
Sorry for exceeding 65 characters in the first comment line on some
recent check-ins. I didn't notice this early.
-Rathijit
On 04/06/2011 05:49 PM, Rathijit Sen wrote:
changeset 01b8bcdb3a1c in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=01b8bcdb3a1c
description
changeset 1f62f3ea6275 in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=1f62f3ea6275
description:
Ruby: Adding figure for common network topologies.
Individual components of the figure were taken from
the GEMS tutorial in ISCA 2005.
diffstat:
changeset 9125ffaa8bfc in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=9125ffaa8bfc
description:
Ruby_overview: Added source and figure for high-level components of
Ruby.
These were taken from the GEMS tutorial in ISCA 2005.
diffstat:
Hi,
I think the directory controller for MOESI_CMP_directory issues a memory
fetch on a GETS in S state. Is this required, or can the current copy be
forwarded (similar to DMA read)?
Thanks,
-Rathijit
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Hi,
We would like to run memtest with x86 FS. Can anyone tell us how to do this?
Thanks,
Rathijit Arka
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Hi,
We are trying to integrate Bochs x86 functional model into M5. In
order to achieve that we are trying to have our own cpu model that does
not use isa_parser generated files. In doing so, we had to remove other
CPU models like AtomicSimpleCPU, TimingSimpleCPU etc, as they depend
upon
Dear Gabe:
We are working on integrating the Bochs x86 cpu model with the M5
framework. We need some testing infrastructure to validate the resulting
system. More specifically we need the following:
1) M5 checkpoints for x86
2) scripts to create above checkpoints
3) regression testing
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