[m5-dev] [PATCH 03 of 11] ruby: fixed dma_cntrl to dma_sequencer connection

[Brad Beckmann]

# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1261412980 28800
# Node ID 39a01746c92648b1191135dfc3563f79a851aaa6
# Parent  72028d922af2e6b59d2ddde4004184dc1b6ea182
ruby: fixed dma_cntrl to dma_sequencer connection
Now the dma_cntrl/sequencer point to eachother similar to the cpu sequencer
and the l1cache cntrl.

diff -r 72028d922af2 -r 39a01746c926 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc       Mon Dec 21 08:29:40 2009 -0800
+++ b/src/mem/ruby/system/DMASequencer.cc       Mon Dec 21 08:29:40 2009 -0800
@@ -19,6 +19,7 @@
 
 void DMASequencer::init()
 {
+  RubyPort::init();
   m_is_busy = false;
   m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
 }
diff -r 72028d922af2 -r 39a01746c926 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py     Mon Dec 21 08:29:40 2009 -0800
+++ b/src/mem/slicc/symbols/StateMachine.py     Mon Dec 21 08:29:40 2009 -0800
@@ -370,7 +370,7 @@
         #
         contains_sequencer = False
         for param in self.config_parameters:
-            if param.name == "sequencer":
+            if param.name == "sequencer" or param.name == "dma_sequencer":
                 contains_sequencer = True
             if param.pointer:
                 code('m_${{param.name}}_ptr = p->${{param.name}};')
@@ -396,7 +396,19 @@
 locked_read_request4 = Address(-1);
 read_counter = 0;
 ''')
+        #
+        # For the DMA controller, pass the sequencer a pointer to the
+        # controller.
+        #
+        if self.ident == "DMA":
+            if not contains_sequencer:
+                self.error("The DMA controller must include the sequencer " \
+                           "configuration parameter")
 
+            code('''
+m_dma_sequencer_ptr->setController(this);
+''')
+            
         code('m_num_controllers++;')
         for var in self.objects:
             if var.ident.find("mandatoryQueue") >= 0:

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