# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1263536244 28800
# Node ID e04160e57f4307f0b1d40524f08f6c1e4b8252ea
# Parent fa362ac18a7a7c2f737fc092f987d94f1beb906a
ruby: Converted MOESI_hammer dma cntrl to new config system
diff -r fa362ac18a7a -r e04160e57f43 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800
@@ -104,6 +104,7 @@
#
l1_cntrl_nodes = []
dir_cntrl_nodes = []
+dma_cntrl_nodes = []
#
# Must create the individual controllers before the network to ensure the
@@ -138,12 +139,15 @@
directory = RubyDirectoryMemory(),
memBuffer = RubyMemoryControl())
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = DMASequencer())
#
# As noted above: Two independent list are track to maintain the order of
# nodes/controllers assumed by the ruby network
#
l1_cntrl_nodes.append(l1_cntrl)
dir_cntrl_nodes.append(dir_cntrl)
+ dma_cntrl_nodes.append(dma_cntrl)
#
# Finally tie the memtester ports to the correct system ports
@@ -157,7 +161,8 @@
# constructor.
#
network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
- dir_cntrl_nodes))
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes))
mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
for dir_cntrl in dir_cntrl_nodes])
@@ -166,7 +171,9 @@
network = network,
profiler = RubyProfiler(),
tracer = RubyTracer(),
- debug = RubyDebug(),
+ debug = RubyDebug(filter_string = 'qQin',
+ verbosity_string = 'high',
+ protocol_trace = True),
mem_size_mb = mem_size_mb)
diff -r fa362ac18a7a -r e04160e57f43 src/mem/protocol/MOESI_hammer-dma.sm
--- a/src/mem/protocol/MOESI_hammer-dma.sm Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-dma.sm Thu Jan 14 22:17:24 2010 -0800
@@ -28,7 +28,8 @@
machine(DMA, "DMA Controller")
-: int request_latency = 6
+: DMASequencer * dma_sequencer,
+ int request_latency = 6
{
MessageBuffer responseFromDir, network="From", virtual_network="4",
ordered="true", no_vector="true";
@@ -47,20 +48,14 @@
Ack, desc="DMA write to memory completed";
}
- external_type(DMASequencer) {
- void ackCallback();
- void dataCallback(DataBlock);
- }
-
MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- DMASequencer dma_sequencer,
factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
State cur_state, no_vector="true";
State getState(Address addr) {
return cur_state;
}
void setState(Address addr, State state) {
- cur_state := state;
+ cur_state := state;
}
out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
diff -r fa362ac18a7a -r e04160e57f43 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/protocol/RubySlicc_Types.sm Thu Jan 14 22:17:24 2010 -0800
@@ -122,6 +122,11 @@
}
+external_type(DMASequencer) {
+ void ackCallback();
+ void dataCallback(DataBlock);
+}
+
external_type(TimerTable, inport="yes") {
bool isReady();
Address readyAddress();
diff -r fa362ac18a7a -r e04160e57f43 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/system/DMASequencer.cc Thu Jan 14 22:17:24 2010 -0800
@@ -8,6 +8,10 @@
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/system/System.hh"
+//
+// Fix me: This code needs comments!
+//
+
DMASequencer::DMASequencer(const Params *p)
: RubyPort(p)
{
@@ -15,6 +19,7 @@
void DMASequencer::init()
{
+ RubyPort::init();
m_is_busy = false;
m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
}
@@ -58,11 +63,16 @@
msg.getLineAddress() = line_address(msg.getPhysicalAddress());
msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
int offset = paddr & m_data_block_mask;
+
msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
len :
RubySystem::getBlockSizeBytes() - offset;
- if (write)
+
+ if (write) {
msg.getDataBlk().setData(data, offset, msg.getLen());
+ }
+
+ assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg);
active_request.bytes_issued += msg.getLen();
@@ -82,14 +92,18 @@
SequencerMsg msg;
msg.getPhysicalAddress() = Address(active_request.start_paddr +
active_request.bytes_completed);
+
assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
msg.getLineAddress() = line_address(msg.getPhysicalAddress());
+
msg.getType() = (active_request.write ? SequencerRequestType_ST :
SequencerRequestType_LD);
+
msg.getLen() = (active_request.len -
active_request.bytes_completed <
RubySystem::getBlockSizeBytes() ?
active_request.len - active_request.bytes_completed :
RubySystem::getBlockSizeBytes());
+
if (active_request.write) {
msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
0, msg.getLen());
@@ -97,6 +111,8 @@
} else {
msg.getType() = SequencerRequestType_LD;
}
+
+ assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg);
active_request.bytes_issued += msg.getLen();
}
diff -r fa362ac18a7a -r e04160e57f43 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/slicc/symbols/StateMachine.py Thu Jan 14 22:17:24 2010 -0800
@@ -38,6 +38,7 @@
"Sequencer": "RubySequencer",
"DirectoryMemory": "RubyDirectoryMemory",
"MemoryControl": "RubyMemoryControl",
+ "DMASequencer": "DMASequencer"
}
class StateMachine(Symbol):
@@ -369,7 +370,7 @@
#
contains_sequencer = False
for param in self.config_parameters:
- if param.name == "sequencer":
+ if param.name == "sequencer" or param.name == "dma_sequencer":
contains_sequencer = True
if param.pointer:
code('m_${{param.name}}_ptr = p->${{param.name}};')
@@ -395,7 +396,19 @@
locked_read_request4 = Address(-1);
read_counter = 0;
''')
+ #
+ # For the DMA controller, pass the sequencer a pointer to the
+ # controller.
+ #
+ if self.ident == "DMA":
+ if not contains_sequencer:
+ self.error("The DMA controller must include the sequencer " \
+ "configuration parameter")
+ code('''
+m_dma_sequencer_ptr->setController(this);
+''')
+
code('m_num_controllers++;')
for var in self.objects:
if var.ident.find("mandatoryQueue") >= 0:
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