# HG changeset patch # User Brad Beckmann <brad.beckm...@amd.com> # Date 1263536246 28800 # Node ID f5f1581d5b7c5d3443cd0792ec20a8bddfc670d5 # Parent 01bab1b7fc3c1da1d60c386999ba940ed773bab5 ruby: Ruby tester now manages data values dynamically
Instead of relying on static data and ugly internal copying of M5 data into the ruby_request, the ruby tester now creates and destroys it's data...this is much cleaner and consistent with other M5 cpu objects. diff -r 01bab1b7fc3c -r f5f1581d5b7c src/cpu/rubytest/Check.cc --- a/src/cpu/rubytest/Check.cc Thu Jan 14 22:17:26 2010 -0800 +++ b/src/cpu/rubytest/Check.cc Thu Jan 14 22:17:26 2010 -0800 @@ -81,7 +81,6 @@ Request::Flags flags; flags.set(Request::PREFETCH); - uint8_t dummyStackdata = 0; // // Prefetches are assumed to be 0 sized @@ -111,7 +110,6 @@ } PacketPtr pkt = new Packet(req, cmd, port->idx); - pkt->dataStatic(&dummyStackdata); // // push the subblock onto the sender state. The sequencer will update the @@ -122,6 +120,12 @@ if (port->sendTiming(pkt)) { DPRINTF(RubyTest, "successfully initiated prefetch.\n"); } else { + // + // If the packet did not issue, must delete + // + delete pkt->senderState; + delete pkt->req; + delete pkt; DPRINTF(RubyTest, "prefetch initiation failed because Port was busy.\n"); } } @@ -136,7 +140,6 @@ (m_tester_ptr->getCpuPort(random() % m_num_cpu_sequencers)); Request::Flags flags; - uint8_t writeData = m_value + m_store_count; // // Create the particular address for the next byte to be written @@ -164,7 +167,14 @@ // } PacketPtr pkt = new Packet(req, cmd, port->idx); - pkt->dataStatic(&writeData); + uint8_t* writeData = new uint8_t; + *writeData = m_value + m_store_count; + pkt->dataDynamic(writeData); + + DPRINTF(RubyTest, + "data 0x%x check 0x%x\n", + *(pkt->getPtr<uint8_t>()), + *writeData); // // push the subblock onto the sender state. The sequencer will update the @@ -179,6 +189,13 @@ (TesterStatus_to_string(m_status)).c_str()); m_status = TesterStatus_Action_Pending; } else { + // + // If the packet did not issue, must delete + // Note: No need to delete the data, the packet destructor will delete it + // + delete pkt->senderState; + delete pkt->req; + delete pkt; DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n"); } @@ -197,7 +214,6 @@ (m_tester_ptr->getCpuPort(random() % m_num_cpu_sequencers)); Request::Flags flags; - uint8_t dummyStackdata = 0; // // Checks are sized depending on the number of bytes written @@ -216,7 +232,8 @@ } PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx); - pkt->dataStatic(&dummyStackdata); + uint8_t* dataArray = new uint8_t[CHECK_SIZE]; + pkt->dataDynamicArray(dataArray); // // push the subblock onto the sender state. The sequencer will update the @@ -231,6 +248,13 @@ (TesterStatus_to_string(m_status)).c_str()); m_status = TesterStatus_Check_Pending; } else { + // + // If the packet did not issue, must delete + // Note: No need to delete the data, the packet destructor will delete it + // + delete pkt->senderState; + delete pkt->req; + delete pkt; DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n"); } diff -r 01bab1b7fc3c -r f5f1581d5b7c src/cpu/rubytest/RubyTester.cc --- a/src/cpu/rubytest/RubyTester.cc Thu Jan 14 22:17:26 2010 -0800 +++ b/src/cpu/rubytest/RubyTester.cc Thu Jan 14 22:17:26 2010 -0800 @@ -107,19 +107,21 @@ // RubyTester::SenderState* senderState = static_cast<RubyTester::SenderState*>(pkt->senderState); - SubBlock* data = senderState->subBlock; - assert(data != NULL); + SubBlock* subblock = senderState->subBlock; + assert(subblock != NULL); // pop the sender state from the packet pkt->senderState = senderState->saved; delete senderState; - tester->hitCallback(idx, data); + tester->hitCallback(idx, subblock); // - // Now that the tester has completed, delete the sublock and return + // Now that the tester has completed, delete the sublock, packet and return // - delete data; + delete subblock; + delete pkt->req; + delete pkt; return true; } _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev