-----Original Message-----
From: g...@cmdmail.amd.com [mailto:g...@cmdmail.amd.com]
Sent: Monday, November 09, 2009 10:33 AM
To: Beckmann, Brad
Subject: [PATCH 29 of 31] ruby: Hammer ruby configuration support
# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1257791384 28800
# Node ID 09a27a0cb56e034f00fbd9d36b2aa2ee137ded63
# Parent c545ad8a3b16ec5d8e76eaf290624dfa65cc0c4b
ruby: Hammer ruby configuration support
diff -r c545ad8a3b16 -r 09a27a0cb56e
src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Mon Nov 09 10:29:43 2009
-0800
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Mon Nov 09 10:29:44 2009
-0800
@@ -140,7 +140,7 @@
TBETable TBEs, template_hack="<L1Cache_TBE>";
CacheMemory L1IcacheMemory,
factory='RubySystem::getCache(m_cfg["icache"])';
CacheMemory L1DcacheMemory,
factory='RubySystem::getCache(m_cfg["dcache"])';
- CacheMemory L2cacheMemory,
factory='RubySystem::getCache(m_cfg["cache"])';
+ CacheMemory L2cacheMemory,
factory='RubySystem::getCache(m_cfg["l2cache"])';
Entry getCacheEntry(Address addr), return_by_ref="yes" {
if (L2cacheMemory.isTagPresent(addr)) {
diff -r c545ad8a3b16 -r 09a27a0cb56e
src/mem/ruby/config/MOESI_hammer-homogeneous.rb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/config/MOESI_hammer-homogeneous.rb Mon Nov 09
10:29:44 2009 -0800
@@ -0,0 +1,109 @@
+#!/usr/bin/ruby
+#
+# Creates multiple on-chip nodes with three level of cache.
+#
+
+require "cfg.rb"
+
+RubySystem.reset
+
+# default values
+
+num_cores = 2
+l1_cache_size_bytes = 32768
+l1_cache_assoc = 2
+l1_cache_latency = 3
+l2_cache_size_bytes = 1048576
+l2_cache_assoc = 16
+l2_cache_latency = 15
+num_memories = 2
+memory_size_mb = 1024
+num_dma = 0
+use_map = false
+map_levels = 4
+protocol = "MOESI_hammer"
+
+# check for overrides
+
+
+for i in 0..$*.size-1 do
+ if $*[i] == "-c"
+ protocol = $*[i+1]
+ i = i+1
+ elsif $*[i] == "-p"
+ num_cores = $*[i+1].to_i
+ i = i+1
+ elsif $*[i] == "-m"
+ num_memories = $*[i+1].to_i
+ i = i+1
+ elsif $*[i] == "-s"
+ memory_size_mb = $*[i+1].to_i
+ i = i + 1
+ elsif $*[i] == "-U"
+ use_map = $*[i+1]
+ i = i + 1
+ elsif $*[i] == "-C"
+ l1_cache_size_bytes = $*[i+1].to_i
+ i = i + 1
+ elsif $*[i] == "-A"
+ l1_cache_assoc = $*[i+1].to_i
+ i = i + 1
+ elsif $*[i] == "-M"
+ map_levels = $*[i+1].to_i
+ i = i + 1
+ elsif $*[i] == "-D"
+ num_dma = $*[i+1].to_i
+ i = i + 1
+ end
+end
+
+net_ports = Array.new
+iface_ports = Array.new
+
+assert(protocol == "MOESI_hammer", __FILE__ + " cannot be used with
protocol " + protocol)
+
+require protocol+".rb"
+
+num_cores.times { |n|
+ icache = SetAssociativeCache.new("l1i_"+n.to_s,
+ l1_cache_size_bytes,
+ l1_cache_latency,
+ l1_cache_assoc,
+ "PSEUDO_LRU")
+ dcache = SetAssociativeCache.new("l1d_"+n.to_s,
+ l1_cache_size_bytes,
+ l1_cache_latency,
+ l1_cache_assoc,
+ "PSEUDO_LRU")
+ l2cache = SetAssociativeCache.new("l2u_"+n.to_s,
+ l2_cache_size_bytes,
+ l2_cache_latency,
+ l2_cache_assoc,
+ "PSEUDO_LRU")
+ sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache)
+ iface_ports << sequencer
+ net_ports <<
MOESI_hammer_CacheController.new("L1CacheController_"+n.to_s,
+ "L1Cache",
+ icache,
+ dcache,
+ l2cache,
+ sequencer)
+}
+num_memories.times { |n|
+ directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s,
memory_size_mb/num_memories)
+ memory_control = MemoryControl.new("MemoryControl_"+n.to_s)
+ net_ports <<
MOESI_hammer_DirectoryController.new("DirectoryController_"+n.to_s,
+ "Directory",
+ directory,
+ memory_control)
+}
+num_dma.times { |n|
+ dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
+ iface_ports << dma_sequencer
+ net_ports << MOESI_hammer_DMAController.new("DMAController_"+n.to_s,
"DMA", dma_sequencer)
+}
+
+topology = CrossbarTopology.new("theTopology", net_ports)
+on_chip_net = Network.new("theNetwork", topology)
+
+RubySystem.init(iface_ports, on_chip_net)
diff -r c545ad8a3b16 -r 09a27a0cb56e src/mem/ruby/config/MOESI_hammer.rb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/config/MOESI_hammer.rb Mon Nov 09 10:29:44 2009
-0800
@@ -0,0 +1,42 @@
+
+require "util.rb"
+
+class MOESI_hammer_CacheController < L1CacheController
+ attr :cache
+ def initialize(obj_name, mach_type, icache, dcache, l2cache,
sequencer)
+ super(obj_name, mach_type, [icache, dcache, l2cache], sequencer)
+ @icache = icache
+ @dcache = dcache
+ @l2cache = l2cache
+ end
+ def argv()
+ vec = super()
+ vec += " icache " + @icache.obj_name
+ vec += " dcache " + @dcache.obj_name
+ vec += " l2cache " + @l2cache.obj_name
+ vec += " issue_latency "+issue_latency.to_s
+ vec += " cache_response_latency "+cache_response_latency.to_s
+ end
+
+end
+
+class MOESI_hammer_DirectoryController < DirectoryController
+ def initialize(obj_name, mach_type, directory, memory_control)
+ super(obj_name, mach_type, directory, memory_control)
+ end
+ def argv()
+ vec = super()
+ vec += " memory_controller_latency "+memory_controller_latency.to_s
+ vec += " memory_latency "+memory_controller_latency.to_s
+ end
+end
+
+class MOESI_hammer_DMAController < DMAController
+ def initialize(obj_name, mach_type, dma_sequencer)
+ super(obj_name, mach_type, dma_sequencer)
+ end
+ def argv()
+ vec = super
+ vec += " request_latency "+request_latency.to_s
+ end
+end
diff -r c545ad8a3b16 -r 09a27a0cb56e src/mem/ruby/config/defaults.rb
--- a/src/mem/ruby/config/defaults.rb Mon Nov 09 10:29:43 2009 -0800
+++ b/src/mem/ruby/config/defaults.rb Mon Nov 09 10:29:44 2009 -0800
@@ -167,6 +167,18 @@
default_param :response_latency, Integer, 6
end
+## MOESI_hammer protocol
+
+class MOESI_hammer_CacheController < L1CacheController
+ default_param :issue_latency, Integer, 2
+ default_param :cache_response_latency, Integer, 12
+end
+
+class MOESI_hammer_DirectoryController < DirectoryController
+ default_param :memory_controller_latency, Integer, 12
+ default_param :memory_latency, Integer, 50
+end
+
class RubySystem
# Random seed used by the simulation. If set to "rand", the seed
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