The dynamic instruction object is really just the dynamic information
associated with an instruction, as apposed to the static instruction
object that gets reused. Strictly speaking there's no guarantee that an
arbitrary dynamic instruction will always use timing mode, but all the
CPU models we
I think you stated it pretty accurately, Gabe. It looks like the
base_dyn_inst.hh file is only used in o3, ozone, and checker, and of
those only o3 is really being used right now.
Steve
On Thu, Jul 22, 2010 at 12:56 AM, Gabe Black gbl...@eecs.umich.edu wrote:
The dynamic instruction object is
so base_dyn_inst is always used timing memory - I assumed so but just wanted
to confirm this to make sure that read function,
BaseDynInstImpl::read(Addr addr, T data, unsigned flags)
'data' argument isn't really doing anything but being a placeholder for func
sig matching in xc interface. -- is
It looks like the right place to place the code that checks for a fault and
calls the CPU read/write function would be
BaseDynInstImpl::finishTranslation().
All the code to make this work seems to be there already. If it hits in the
TLB, then TheISA::TLB::translateTiming() should call
Thanks, Tim
It looks like the for the DTLB translation, some code is there to handle
this but not complete, for the ISAs that does hardware page table walk.
cpu/base_dyn_inst.hh
BaseDynInstImpl::read(Addr addr, T data, unsigned flags)
{
...
initiateTranslation(req, sreqLow, sreqHigh, NULL,
I think you've mostly interpretted this correctly. The instructions
aren't retried if the translation fails, they just hang around and
wait for it. The check if fault == NoFault will work if the
translation is finished by the time initiateTranslation is done.
That's true for everything we
Hi,
This question is regarding the changeset (
http://repo.m5sim.org/m5?cmd=changeset;node=a123bd350935).
This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish
It looks like even in the event of TLB miss, TLB-walk does not delay
Hi Min,
The way that the TLB deals with a timing translation is specific to each
ISA. I don't have much experience with anything other than Power but
for that ISA, yes, you're correct. The timing translation is just a
wrapper around the atomic translation. It seems from a quick check that
