I've run into a buggy interaction for the ARM ISA between a TBH (or TBB)
instruction and a dependent memory operation (that gets squashed) in the O3
model leading to erroneous behavior when diffed against the Atomic model.
The TBH instruction is a table-based branch that has to index into memory
on #5, is it the case that the branch is always mispredicted on a
squashDueToMemOrder() ??? I would think so because you havent got the branch
back right?
Sounds like there is a couple issues to tackle:
1) Where to start fetching while you wait for resolution?
--- a: look in the BTB for a
