changeset 00ea9430643b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00ea9430643b
description:
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal
loads
that don't writeback a register. Previously prefetches were supposed to
call
prefetch() on the exection context, so they executed with execute()
methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all
the CPUs
are blank, meaning that they get executed, but don't actually do
anything.
On Alpha dead cache copy code was removed and prefetches are now normal
ops.
They count as executed operations, but still don't do anything and
IsMemRef is
not longer set on them.
On ARM IsDataPrefetch or IsInstructionPreftech is now set on all
prefetch
instructions. The timing simple CPU doesn't try to do anything special
for
prefetches now and they execute with the normal memory code path.
diffstat:
src/arch/alpha/isa/decoder.isa | 16 +----
src/arch/alpha/isa/mem.isa | 9 +-
src/arch/arm/isa/insts/ldr.isa | 27 ++++---
src/arch/mips/isa/formats/mem.isa | 7 +-
src/cpu/base_dyn_inst.hh | 5 -
src/cpu/base_dyn_inst_impl.hh | 67 -------------------
src/cpu/checker/cpu.cc | 12 ---
src/cpu/checker/cpu.hh | 14 ----
src/cpu/exec_context.hh | 9 --
src/cpu/inorder/cpu.cc | 15 ----
src/cpu/inorder/cpu.hh | 10 --
src/cpu/inorder/inorder_dyn_inst.cc | 32 ---------
src/cpu/inorder/inorder_dyn_inst.hh | 4 -
src/cpu/inorder/resource.hh | 6 -
src/cpu/inorder/resources/cache_unit.cc | 37 ----------
src/cpu/inorder/resources/cache_unit.hh | 4 -
src/cpu/ozone/cpu.hh | 14 ----
src/cpu/ozone/cpu_impl.hh | 89 -------------------------
src/cpu/simple/base.cc | 112 --------------------------------
src/cpu/simple/base.hh | 7 --
src/cpu/simple/timing.cc | 15 +++-
src/cpu/static_inst.hh | 2 +
22 files changed, 41 insertions(+), 472 deletions(-)
diffs (truncated from 807 to 300 lines):
diff -r ba11187e2582 -r 00ea9430643b src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Mon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/alpha/isa/decoder.isa Mon Nov 08 13:58:22 2010 -0600
@@ -47,11 +47,6 @@
0x23: ldt({{ Fa = Mem.df; }});
0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
-#ifdef USE_COPY
- 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
- {{ fault = xc->copySrcTranslate(EA); }},
- inst_flags = [IsMemRef, IsLoad, IsCopy]);
-#endif
}
format LoadOrPrefetch {
@@ -71,11 +66,6 @@
0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
0x27: stt({{ Mem.df = Fa; }});
-#ifdef USE_COPY
- 0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
- {{ fault = xc->copy(EA); }},
- inst_flags = [IsMemRef, IsStore,
IsCopy]);
-#endif
}
format StoreCond {
@@ -788,10 +778,8 @@
format MiscPrefetch {
0xf800: wh64({{ EA = Rb & ~ULL(63); }},
- {{ xc->writeHint(EA, 64, memAccessFlags); }},
- mem_flags = PREFETCH,
- inst_flags = [IsMemRef, IsDataPrefetch,
- IsStore, MemWriteOp]);
+ {{ ; }},
+ mem_flags = PREFETCH);
}
format BasicOperate {
diff -r ba11187e2582 -r 00ea9430643b src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Mon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/alpha/isa/mem.isa Mon Nov 08 13:58:22 2010 -0600
@@ -396,6 +396,7 @@
%(op_rd)s;
%(ea_code)s;
+ warn_once("Prefetch instrutions is Alpha do not do anything\n");
if (fault == NoFault) {
%(memacc_code)s;
}
@@ -404,6 +405,8 @@
}
}};
+// Prefetches in Alpha don't actually do anything
+// They just build an effective address and complete
def template MiscInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@@ -530,12 +533,10 @@
inst_flags = makeList(inst_flags)
pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
- pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
- 'IsDataPrefetch', 'MemReadOp']
+ pf_inst_flags = inst_flags
(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
- LoadStoreBase(name, Name + 'Prefetch', ea_code,
- 'xc->prefetch(EA, memAccessFlags);',
+ LoadStoreBase(name, Name + 'Prefetch', ea_code, ';',
pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
header_output += pf_header_output
diff -r ba11187e2582 -r 00ea9430643b src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Mon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/arm/isa/insts/ldr.isa Mon Nov 08 13:58:22 2010 -0600
@@ -161,8 +161,13 @@
if self.user:
self.memFlags.append("ArmISA::TLB::UserMode")
- if self.flavor == "prefetch":
+ self.instFlags = []
+ if self.flavor == "dprefetch":
self.memFlags.append("Request::PREFETCH")
+ self.instFlags = ['IsDataPrefetch']
+ elif self.flavor == "iprefetch":
+ self.memFlags.append("Request::PREFETCH")
+ self.instFlags = ['IsInstPrefetch']
elif self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
elif self.flavor == "normal":
@@ -185,7 +190,7 @@
self.codeBlobs["ea_code"] = eaCode
# Code that actually handles the access
- if self.flavor == "prefetch":
+ if self.flavor == "dprefetch" or self.flavor == "iprefetch":
accCode = 'uint64_t temp = Mem%s; temp = temp;'
elif self.flavor == "fp":
accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
@@ -200,7 +205,7 @@
wbDecl = None
if self.writeback:
wbDecl = self.wbDecl
- self.emitHelper(base, wbDecl)
+ self.emitHelper(base, wbDecl, self.instFlags)
def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
@@ -325,11 +330,11 @@
RfeInst(mnem, False, False, True).emit()
RfeInst(mnem, False, False, False).emit()
- def buildPrefetches(mnem):
- LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit()
- LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit()
- LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit()
- LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit()
+ def buildPrefetches(mnem, type):
+ LoadReg(mnem, False, False, False, size=1, flavor=type).emit()
+ LoadImm(mnem, False, False, False, size=1, flavor=type).emit()
+ LoadReg(mnem, False, True, False, size=1, flavor=type).emit()
+ LoadImm(mnem, False, True, False, size=1, flavor=type).emit()
buildLoads("ldr")
buildLoads("ldrt", user=True)
@@ -346,9 +351,9 @@
buildRfeLoads("rfe")
- buildPrefetches("pld")
- buildPrefetches("pldw")
- buildPrefetches("pli")
+ buildPrefetches("pld", "dprefetch")
+ buildPrefetches("pldw", "dprefetch")
+ buildPrefetches("pli", "iprefetch")
LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()
diff -r ba11187e2582 -r 00ea9430643b src/arch/mips/isa/formats/mem.isa
--- a/src/arch/mips/isa/formats/mem.isa Mon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/mips/isa/formats/mem.isa Mon Nov 08 13:58:22 2010 -0600
@@ -452,7 +452,7 @@
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Addr EA;
+ Addr EA M5_VAR_USED = 0;
Fault fault = NoFault;
%(fp_enable_check)s;
@@ -577,12 +577,11 @@
def format Prefetch(ea_code = {{ EA = Rs + disp; }},
mem_flags = [], pf_flags = [], inst_flags = []) {{
pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
- pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
- 'IsDataPrefetch', 'MemReadOp']
+ pf_inst_flags = inst_flags
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code,
- 'xc->prefetch(EA, memAccessFlags);',
+ 'warn_once("Prefetching not implemented for MIPS\\n");',
pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
}};
diff -r ba11187e2582 -r 00ea9430643b src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Mon Nov 08 13:58:22 2010 -0600
+++ b/src/cpu/base_dyn_inst.hh Mon Nov 08 13:58:22 2010 -0600
@@ -150,11 +150,6 @@
/** Finish a DTB address translation. */
void finishTranslation(WholeTranslationState *state);
- void prefetch(Addr addr, unsigned flags);
- void writeHint(Addr addr, int size, unsigned flags);
- Fault copySrcTranslate(Addr src);
- Fault copy(Addr dest);
-
/** @todo: Consider making this private. */
public:
/** The sequence number of the instruction. */
diff -r ba11187e2582 -r 00ea9430643b src/cpu/base_dyn_inst_impl.hh
--- a/src/cpu/base_dyn_inst_impl.hh Mon Nov 08 13:58:22 2010 -0600
+++ b/src/cpu/base_dyn_inst_impl.hh Mon Nov 08 13:58:22 2010 -0600
@@ -196,73 +196,6 @@
template <class Impl>
void
-BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
-{
- // This is the "functional" implementation of prefetch. Not much
- // happens here since prefetches don't affect the architectural
- // state.
-/*
- // Generate a MemReq so we can translate the effective address.
- MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
- req->asid = asid;
-
- // Prefetches never cause faults.
- fault = NoFault;
-
- // note this is a local, not BaseDynInst::fault
- Fault trans_fault = cpu->translateDataReadReq(req);
-
- if (trans_fault == NoFault && !(req->isUncacheable())) {
- // It's a valid address to cacheable space. Record key MemReq
- // parameters so we can generate another one just like it for
- // the timing access without calling translate() again (which
- // might mess up the TLB).
- effAddr = req->vaddr;
- physEffAddr = req->paddr;
- memReqFlags = req->flags;
- } else {
- // Bogus address (invalid or uncacheable space). Mark it by
- // setting the eff_addr to InvalidAddr.
- effAddr = physEffAddr = MemReq::inval_addr;
- }
-
- if (traceData) {
- traceData->setAddr(addr);
- }
-*/
-}
-
-template <class Impl>
-void
-BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
-{
- // Not currently supported.
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-template <class Impl>
-Fault
-BaseDynInst<Impl>::copySrcTranslate(Addr src)
-{
- // Not currently supported.
- return NoFault;
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-template <class Impl>
-Fault
-BaseDynInst<Impl>::copy(Addr dest)
-{
- // Not currently supported.
- return NoFault;
-}
-
-template <class Impl>
-void
BaseDynInst<Impl>::dump()
{
cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
diff -r ba11187e2582 -r 00ea9430643b src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Mon Nov 08 13:58:22 2010 -0600
+++ b/src/cpu/checker/cpu.cc Mon Nov 08 13:58:22 2010 -0600
@@ -134,18 +134,6 @@
*/
}
-Fault
-CheckerCPU::copySrcTranslate(Addr src)
-{
- panic("Unimplemented!");
-}
-
-Fault
-CheckerCPU::copy(Addr dest)
-{
- panic("Unimplemented!");
-}
-
template <class T>
Fault
CheckerCPU::read(Addr addr, T &data, unsigned flags)
diff -r ba11187e2582 -r 00ea9430643b src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Mon Nov 08 13:58:22 2010 -0600
+++ b/src/cpu/checker/cpu.hh Mon Nov 08 13:58:22 2010 -0600
@@ -178,20 +178,6 @@
void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
- void prefetch(Addr addr, unsigned flags)
- {
- // need to do this...
- }
-
- void writeHint(Addr addr, int size, unsigned flags)
- {
- // need to do this...
- }
-
- Fault copySrcTranslate(Addr src);
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