changeset be6658746087 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=be6658746087
description:
ARM: Move the remaining microops out of the decoder and into the ISA
desc.
diffstat:
3 files changed, 31 insertions(+), 18 deletions(-)
src/arch/arm/isa/decoder.isa | 16 ++--------------
src/arch/arm/isa/formats/macromem.isa | 27 +++++++++++++++++++++++++++
src/arch/arm/isa/formats/util.isa | 6 ++----
diffs (92 lines):
diff -r 7f10d636910b -r be6658746087 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Wed Jul 08 23:02:19 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Wed Jul 08 23:02:19 2009 -0700
@@ -37,19 +37,8 @@
// in the ARM ISA specification document starting with Table B.1 or 3-1
//
//
-decode COND_CODE default Unknown::unknown() {
- 0xf: decode COND_CODE {
- 0x1: decode OPCODE {
- // Just a simple trick to allow us to specify our new uops here
- 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
- 'IsMicroop');
- 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
- Rlo = Fd.ud & 0xffffffff; }},
- 'IsMicroop');
- }
- default: Unknown::unknown(); // TODO: Ignore other NV space for now
- }
-default: decode ENCODING {
+
+decode ENCODING default Unknown::unknown() {
format DataOp {
0x0: decode SEVEN_AND_FOUR {
1: decode MISC_OPCODE {
@@ -440,5 +429,4 @@
}
}
}
-}
diff -r 7f10d636910b -r be6658746087 src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa Wed Jul 08 23:02:19 2009 -0700
+++ b/src/arch/arm/isa/formats/macromem.isa Wed Jul 08 23:02:19 2009 -0700
@@ -130,6 +130,33 @@
////////////////////////////////////////////////////////////////////
//
+// Moving to/from double floating point registers
+//
+
+let {{
+ microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop',
+ 'PredOp',
+ {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+ microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop',
+ 'PredOp',
+ {'code': '''Rhi = bits(Fd.ud, 63, 32);
+ Rlo = bits(Fd.ud, 31, 0);''',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+ header_output = BasicDeclare.subst(microMvtdUopIop) + \
+ BasicDeclare.subst(microMvfdUopIop)
+ decoder_output = BasicConstructor.subst(microMvtdUopIop) + \
+ BasicConstructor.subst(microMvfdUopIop)
+ exec_output = PredOpExecute.subst(microMvtdUopIop) + \
+ PredOpExecute.subst(microMvfdUopIop)
+}};
+
+////////////////////////////////////////////////////////////////////
+//
// Macro Memory-format instructions
//
diff -r 7f10d636910b -r be6658746087 src/arch/arm/isa/formats/util.isa
--- a/src/arch/arm/isa/formats/util.isa Wed Jul 08 23:02:19 2009 -0700
+++ b/src/arch/arm/isa/formats/util.isa Wed Jul 08 23:02:19 2009 -0700
@@ -106,18 +106,16 @@
emit_ldfstf_uops(StaticInstPtr* microOps, int index, ExtMachInst machInst,
bool loadop, bool up, int32_t disp)
{
- MachInst newMachInst = machInst & 0xf000f000;
-
if (loadop)
{
microOps[index++] = new MicroLdrUop(machInst, 19, RN, disp);
microOps[index++] =
new MicroLdrUop(machInst, 18, RN, disp + (up ? 4 : -4));
- microOps[index++] = new Mvtd_uop(newMachInst);
+ microOps[index++] = new MicroMvtdUop(machInst);
}
else
{
- microOps[index++] = new Mvfd_uop(newMachInst);
+ microOps[index++] = new MicroMvfdUop(machInst);
microOps[index++] = new MicroStrUop(machInst, 19, RN, disp);
microOps[index++] =
new MicroStrUop(machInst, 18, RN, disp + (up ? 4 : -4));
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