changeset 07ba4754ae0a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=07ba4754ae0a
description:
O3: Fix corner cases where multiple squashes/fetch redirects overwrite
timebuf.
diffstat:
src/cpu/o3/iew_impl.hh | 69 ++++++++++++++++++++++++++------------------
src/cpu/o3/lsq_unit_impl.hh | 4 +-
2 files changed, 42 insertions(+), 31 deletions(-)
diffs (151 lines):
diff -r bb38f0c47ade -r 07ba4754ae0a src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Tue Jan 18 16:30:05 2011 -0600
+++ b/src/cpu/o3/iew_impl.hh Tue Jan 18 16:30:05 2011 -0600
@@ -452,20 +452,24 @@
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
"[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
- toCommit->squash[tid] = true;
- toCommit->squashedSeqNum[tid] = inst->seqNum;
- toCommit->mispredPC[tid] = inst->instAddr();
- toCommit->branchMispredict[tid] = true;
- toCommit->mispredictInst[tid] = inst;
+ if (toCommit->squash[tid] == false ||
+ inst->seqNum < toCommit->squashedSeqNum[tid]) {
+ toCommit->squash[tid] = true;
+ toCommit->squashedSeqNum[tid] = inst->seqNum;
+ toCommit->mispredPC[tid] = inst->instAddr();
+ toCommit->branchMispredict[tid] = true;
+ toCommit->branchTaken[tid] = inst->pcState().branching();
- toCommit->branchTaken[tid] = inst->pcState().branching();
- TheISA::PCState pc = inst->pcState();
- TheISA::advancePC(pc, inst->staticInst);
- toCommit->pc[tid] = pc;
+ TheISA::PCState pc = inst->pcState();
+ TheISA::advancePC(pc, inst->staticInst);
- toCommit->includeSquashInst[tid] = false;
+ toCommit->pc[tid] = pc;
+ toCommit->mispredictInst[tid] = inst;
+ toCommit->includeSquashInst[tid] = false;
- wroteToTimeBuffer = true;
+ wroteToTimeBuffer = true;
+ }
+
}
template<class Impl>
@@ -475,16 +479,19 @@
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
- toCommit->squash[tid] = true;
- toCommit->squashedSeqNum[tid] = inst->seqNum;
- TheISA::PCState pc = inst->pcState();
- TheISA::advancePC(pc, inst->staticInst);
- toCommit->pc[tid] = pc;
- toCommit->branchMispredict[tid] = false;
+ if (toCommit->squash[tid] == false ||
+ inst->seqNum < toCommit->squashedSeqNum[tid]) {
+ toCommit->squash[tid] = true;
+ toCommit->squashedSeqNum[tid] = inst->seqNum;
+ TheISA::PCState pc = inst->pcState();
+ TheISA::advancePC(pc, inst->staticInst);
+ toCommit->pc[tid] = pc;
+ toCommit->branchMispredict[tid] = false;
- toCommit->includeSquashInst[tid] = false;
+ toCommit->includeSquashInst[tid] = false;
- wroteToTimeBuffer = true;
+ wroteToTimeBuffer = true;
+ }
}
template<class Impl>
@@ -493,18 +500,21 @@
{
DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
+ if (toCommit->squash[tid] == false ||
+ inst->seqNum < toCommit->squashedSeqNum[tid]) {
+ toCommit->squash[tid] = true;
- toCommit->squash[tid] = true;
- toCommit->squashedSeqNum[tid] = inst->seqNum;
- toCommit->pc[tid] = inst->pcState();
- toCommit->branchMispredict[tid] = false;
+ toCommit->squashedSeqNum[tid] = inst->seqNum;
+ toCommit->pc[tid] = inst->pcState();
+ toCommit->branchMispredict[tid] = false;
- // Must include the broadcasted SN in the squash.
- toCommit->includeSquashInst[tid] = true;
+ // Must include the broadcasted SN in the squash.
+ toCommit->includeSquashInst[tid] = true;
- ldstQueue.setLoadBlockedHandled(tid);
+ ldstQueue.setLoadBlockedHandled(tid);
- wroteToTimeBuffer = true;
+ wroteToTimeBuffer = true;
+ }
}
template<class Impl>
@@ -788,7 +798,6 @@
}
dispatchStatus[tid] = Squashing;
-
fetchRedirect[tid] = false;
return;
}
@@ -797,7 +806,6 @@
DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
dispatchStatus[tid] = Squashing;
-
emptyRenameInsts(tid);
wroteToTimeBuffer = true;
return;
@@ -1286,6 +1294,7 @@
ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid] ||
+ !toCommit->squash[tid] ||
toCommit->squashedSeqNum[tid] > inst->seqNum) {
if (inst->mispredicted()) {
@@ -1382,6 +1391,7 @@
// iew queue. That way the writeback event will write into the correct
// spot in the queue.
wbNumInst = 0;
+
}
template <class Impl>
@@ -1596,6 +1606,7 @@
ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid] ||
+ !toCommit->squash[tid] ||
toCommit->squashedSeqNum[tid] > inst->seqNum) {
if (inst->mispredicted()) {
diff -r bb38f0c47ade -r 07ba4754ae0a src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Tue Jan 18 16:30:05 2011 -0600
+++ b/src/cpu/o3/lsq_unit_impl.hh Tue Jan 18 16:30:05 2011 -0600
@@ -90,8 +90,8 @@
{
LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
DynInstPtr inst = state->inst;
- DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
- DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
+ DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
+ DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
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