changeset bb38f0c47ade in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=bb38f0c47ade description: O3: Fix mispredicts from non control instructions. The squash inside the fetch unit should not attempt to remove them from the branch predictor as non-control instructions are not pushed into the predictor.
diffstat: src/cpu/o3/comm.hh | 5 ++++- src/cpu/o3/commit_impl.hh | 4 +++- src/cpu/o3/fetch_impl.hh | 10 ++++++++-- src/cpu/o3/iew_impl.hh | 1 + 4 files changed, 16 insertions(+), 4 deletions(-) diffs (95 lines): diff -r 02450f4443ce -r bb38f0c47ade src/cpu/o3/comm.hh --- a/src/cpu/o3/comm.hh Tue Jan 18 16:30:02 2011 -0600 +++ b/src/cpu/o3/comm.hh Tue Jan 18 16:30:05 2011 -0600 @@ -87,6 +87,7 @@ bool squash[Impl::MaxThreads]; bool branchMispredict[Impl::MaxThreads]; + DynInstPtr mispredictInst[Impl::MaxThreads]; bool branchTaken[Impl::MaxThreads]; Addr mispredPC[Impl::MaxThreads]; TheISA::PCState pc[Impl::MaxThreads]; @@ -107,6 +108,7 @@ /** Struct that defines all backwards communication. */ template<class Impl> struct TimeBufStruct { + typedef typename Impl::DynInstPtr DynInstPtr; struct decodeComm { bool squash; bool predIncorrect; @@ -117,6 +119,7 @@ // @todo: Might want to package this kind of branch stuff into a single // struct as it is used pretty frequently. bool branchMispredict; + DynInstPtr mispredictInst; bool branchTaken; Addr mispredPC; TheISA::PCState nextPC; @@ -156,6 +159,7 @@ bool robSquashing; bool branchMispredict; + DynInstPtr mispredictInst; bool branchTaken; Addr mispredPC; TheISA::PCState pc; @@ -175,7 +179,6 @@ InstSeqNum nonSpecSeqNum; // Hack for now to send back an uncached access to the IEW stage. - typedef typename Impl::DynInstPtr DynInstPtr; bool uncached; DynInstPtr uncachedLoad; diff -r 02450f4443ce -r bb38f0c47ade src/cpu/o3/commit_impl.hh --- a/src/cpu/o3/commit_impl.hh Tue Jan 18 16:30:02 2011 -0600 +++ b/src/cpu/o3/commit_impl.hh Tue Jan 18 16:30:05 2011 -0600 @@ -520,6 +520,7 @@ toIEW->commitInfo[tid].robSquashing = true; toIEW->commitInfo[tid].branchMispredict = false; + toIEW->commitInfo[tid].mispredictInst = NULL; toIEW->commitInfo[tid].pc = pc[tid]; } @@ -814,7 +815,8 @@ toIEW->commitInfo[tid].branchMispredict = fromIEW->branchMispredict[tid]; - + toIEW->commitInfo[tid].mispredictInst = + fromIEW->mispredictInst[tid]; toIEW->commitInfo[tid].branchTaken = fromIEW->branchTaken[tid]; diff -r 02450f4443ce -r bb38f0c47ade src/cpu/o3/fetch_impl.hh --- a/src/cpu/o3/fetch_impl.hh Tue Jan 18 16:30:02 2011 -0600 +++ b/src/cpu/o3/fetch_impl.hh Tue Jan 18 16:30:05 2011 -0600 @@ -902,8 +902,14 @@ fromCommit->commitInfo[tid].doneSeqNum, tid); - // Also check if there's a mispredict that happened. - if (fromCommit->commitInfo[tid].branchMispredict) { + // If it was a branch mispredict on a control instruction, update the + // branch predictor with that instruction, otherwise just kill the + // invalid state we generated in after sequence number + assert(!fromCommit->commitInfo[tid].branchMispredict || + fromCommit->commitInfo[tid].mispredictInst); + + if (fromCommit->commitInfo[tid].branchMispredict && + fromCommit->commitInfo[tid].mispredictInst->isControl()) { branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, fromCommit->commitInfo[tid].pc, fromCommit->commitInfo[tid].branchTaken, diff -r 02450f4443ce -r bb38f0c47ade src/cpu/o3/iew_impl.hh --- a/src/cpu/o3/iew_impl.hh Tue Jan 18 16:30:02 2011 -0600 +++ b/src/cpu/o3/iew_impl.hh Tue Jan 18 16:30:05 2011 -0600 @@ -456,6 +456,7 @@ toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->mispredPC[tid] = inst->instAddr(); toCommit->branchMispredict[tid] = true; + toCommit->mispredictInst[tid] = inst; toCommit->branchTaken[tid] = inst->pcState().branching(); TheISA::PCState pc = inst->pcState(); _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev