I went back and checked this out, and this was actually fine. I would
have still liked to have determined that before it went in, but the
problem I had with it was misguided. Good work ARM folks, and sorry for
the hassle.
Gabe
On 01/18/11 15:08, Gabe Black wrote:
I'm pretty sure I mentioned
changeset b2c7e56572a4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b2c7e56572a4
description:
O3: Fix some variable length instruction issues with the O3 CPU and ARM
ISA.
diffstat:
src/arch/arm/predecoder.cc | 15 +++
src/arch/arm/predecoder.hh | 22
I'm pretty sure I mentioned twice that this is likely not the right way
to do this. The ARM predecoder should consume the bytes it has, not
ensure through special behavior in fetch that what it needs will always
be there. I haven't tried it yet, but I remember having concerns that
this would break
