changeset 6776001c9b92 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6776001c9b92 description: X86: Add a check to chks to verify a task state segment descriptor.
diffstat: 2 files changed, 11 insertions(+), 2 deletions(-) src/arch/x86/isa/microasm.isa | 2 +- src/arch/x86/isa/microops/regop.isa | 11 ++++++++++- diffs (40 lines): diff -r b702f4fdf16c -r 6776001c9b92 src/arch/x86/isa/microasm.isa --- a/src/arch/x86/isa/microasm.isa Wed Feb 25 10:16:54 2009 -0800 +++ b/src/arch/x86/isa/microasm.isa Wed Feb 25 10:17:02 2009 -0800 @@ -87,7 +87,7 @@ # Add in symbols for the various checks of segment selectors. for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck", "SoftIntGateCheck", "SSCheck", "IretCheck", "IntCSCheck", - "TRCheck"): + "TRCheck", "TSSCheck"): assembler.symbols[check] = "Seg%s" % check for reg in ("TR", "IDTR"): diff -r b702f4fdf16c -r 6776001c9b92 src/arch/x86/isa/microops/regop.isa --- a/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:16:54 2009 -0800 +++ b/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:17:02 2009 -0800 @@ -235,7 +235,7 @@ enum SegmentSelectorCheck { SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, - SegTRCheck + SegTRCheck, SegTSSCheck }; enum LongModeDescriptorType { @@ -1124,6 +1124,15 @@ fault = new GeneralProtection(selector); } break; + case SegTSSCheck: + if (!desc.p) { + fault = new SegmentNotPresent(selector); + } else if (!(desc.type == 0x9 || + (desc.type == 1 && + m5reg.mode != LongMode))) { + + } + break; default: panic("Undefined segment check type.\\n"); } _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev