changeset 6ed48cba2217 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6ed48cba2217 description: decouple eviction from insertion in the cache.
diffstat: 4 files changed, 6 insertions(+), 6 deletions(-) src/mem/cache/tags/fa_lru.hh | 2 +- src/mem/cache/tags/iic.hh | 2 +- src/mem/cache/tags/lru.cc | 2 +- src/mem/cache/tags/lru.hh | 6 +++--- diffs (196 lines): diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/cache_impl.hh Tue Nov 04 11:35:58 2008 -0500 @@ -319,6 +319,7 @@ incMissCount(pkt); return false; } + tags->insertBlock(pkt->getAddr(), blk); blk->status = BlkValid | BlkReadable; } std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize); @@ -879,7 +880,7 @@ typename Cache<TagStore>::BlkType* Cache<TagStore>::allocateBlock(Addr addr, PacketList &writebacks) { - BlkType *blk = tags->findReplacement(addr, writebacks); + BlkType *blk = tags->findVictim(addr, writebacks); if (blk->isValid()) { Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); @@ -890,6 +891,7 @@ assert(!blk->isWritable()); assert(repl_mshr->needsExclusive()); // too hard to replace block with transient state + // allocation failed, block not inserted return NULL; } else { DPRINTF(Cache, "replacement: replacing %x with %x: %s\n", @@ -903,8 +905,6 @@ } } - // Set tag for new block. Caller is responsible for setting status. - blk->tag = tags->extractTag(addr); return blk; } @@ -937,6 +937,8 @@ tempBlock->set = tags->extractSet(addr); tempBlock->tag = tags->extractTag(addr); DPRINTF(Cache, "using temp block for %x\n", addr); + } else { + tags->insertBlock(addr, blk); } } else { // existing block... probably an upgrade diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/tags/fa_lru.cc --- a/src/mem/cache/tags/fa_lru.cc Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/tags/fa_lru.cc Tue Nov 04 11:35:58 2008 -0500 @@ -207,7 +207,7 @@ } FALRUBlk* -FALRU::findReplacement(Addr addr, PacketList &writebacks) +FALRU::findVictim(Addr addr, PacketList &writebacks) { FALRUBlk * blk = tail; assert(blk->inCache == 0); @@ -226,6 +226,11 @@ } //assert(check()); return blk; +} + +void +FALRU::insertBlock(Addr addr, FALRU::BlkType *blk) +{ } void diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/tags/fa_lru.hh --- a/src/mem/cache/tags/fa_lru.hh Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/tags/fa_lru.hh Tue Nov 04 11:35:58 2008 -0500 @@ -197,7 +197,9 @@ * @param writebacks List for any writebacks to be performed. * @return The block to place the replacement in. */ - FALRUBlk* findReplacement(Addr addr, PacketList & writebacks); + FALRUBlk* findVictim(Addr addr, PacketList & writebacks); + + void insertBlock(Addr addr, BlkType *blk); /** * Return the hit latency of this cache. diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/tags/iic.cc --- a/src/mem/cache/tags/iic.cc Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/tags/iic.cc Tue Nov 04 11:35:58 2008 -0500 @@ -297,7 +297,7 @@ IICTag* -IIC::findReplacement(Addr addr, PacketList &writebacks) +IIC::findVictim(Addr addr, PacketList &writebacks) { DPRINTF(IIC, "Finding Replacement for %x\n", addr); unsigned set = hash(addr); @@ -337,6 +337,11 @@ tag_ptr->re = (void*)repl->add(tag_ptr-tagStore); return tag_ptr; +} + +void +IIC::insertBlock(Addr addr, BlkType* blk) +{ } void diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/tags/iic.hh --- a/src/mem/cache/tags/iic.hh Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/tags/iic.hh Tue Nov 04 11:35:58 2008 -0500 @@ -435,7 +435,9 @@ * @param writebacks List for any writebacks to be performed. * @return The block to place the replacement in. */ - IICTag* findReplacement(Addr addr, PacketList &writebacks); + IICTag* findVictim(Addr addr, PacketList &writebacks); + + void insertBlock(Addr addr, BlkType *blk); /** * Read the data from the internal storage of the given cache block. diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/tags/lru.cc --- a/src/mem/cache/tags/lru.cc Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/tags/lru.cc Tue Nov 04 11:35:58 2008 -0500 @@ -183,12 +183,11 @@ } LRUBlk* -LRU::findReplacement(Addr addr, PacketList &writebacks) +LRU::findVictim(Addr addr, PacketList &writebacks) { unsigned set = extractSet(addr); // grab a replacement candidate LRUBlk *blk = sets[set].blks[assoc-1]; - sets[set].moveToHead(blk); if (blk->isValid()) { replacements[0]++; totalRefs += blk->refCount; @@ -197,7 +196,14 @@ DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n", set, regenerateBlkAddr(blk->tag, set)); - } else if (!blk->isTouched) { + } + return blk; +} + +void +LRU::insertBlock(Addr addr, LRU::BlkType *blk) +{ + if (!blk->isTouched) { tagsInUse++; blk->isTouched = true; if (!warmedUp && tagsInUse.value() >= warmupBound) { @@ -206,7 +212,11 @@ } } - return blk; + // Set tag for new block. Caller is responsible for setting status. + blk->tag = extractTag(addr); + + unsigned set = extractSet(addr); + sets[set].moveToHead(blk); } void diff -r ee56bb539212 -r 6ed48cba2217 src/mem/cache/tags/lru.hh --- a/src/mem/cache/tags/lru.hh Tue Nov 04 11:35:57 2008 -0500 +++ b/src/mem/cache/tags/lru.hh Tue Nov 04 11:35:58 2008 -0500 @@ -180,12 +180,20 @@ LRUBlk* findBlock(Addr addr) const; /** - * Find a replacement block for the address provided. - * @param pkt The request to a find a replacement candidate for. + * Find a block to evict for the address provided. + * @param addr The addr to a find a replacement candidate for. * @param writebacks List for any writebacks to be performed. - * @return The block to place the replacement in. + * @return The candidate block. */ - LRUBlk* findReplacement(Addr addr, PacketList &writebacks); + LRUBlk* findVictim(Addr addr, PacketList &writebacks); + + /** + * Insert the new block into the cache. For LRU this means inserting into + * the MRU position of the set. + * @param addr The address to update. + * @param blk The block to update. + */ + void insertBlock(Addr addr, BlkType *blk); /** * Generate the tag from the given address. _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev