changeset 554d84a850d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=554d84a850d6
description:
ruby: fixed dma mi example to work with multiple dma ports
diffstat:
4 files changed, 18 insertions(+), 11 deletions(-)
src/mem/protocol/MI_example-dir.sm | 24 +++++++++++++++---------
src/mem/protocol/MI_example-dma.sm | 2 ++
src/mem/protocol/MI_example-msg.sm | 1 +
src/mem/ruby/config/MI_example.rb | 2 --
diffs (124 lines):
diff -r 62c628499cd4 -r 554d84a850d6 src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/protocol/MI_example-dir.sm Wed Nov 18 13:55:58 2009 -0800
@@ -1,8 +1,6 @@
machine(Directory, "Directory protocol")
-: int directory_latency,
- int dma_select_low_bit,
- int dma_select_num_bits
+: int directory_latency
{
MessageBuffer forwardFromDir, network="To", virtual_network="2",
ordered="false";
@@ -74,6 +72,7 @@
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Data to be written (DMA write only)";
int Len, desc="...";
+ MachineID DmaRequestor, desc="DMA requestor";
}
external_type(TBETable) {
@@ -243,8 +242,7 @@
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block
and rely on the dma controller to split it up if need be
- out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
- dma_select_low_bit,
dma_select_num_bits));
+ out_msg.Destination.add(TBEs[address].DmaRequestor);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
@@ -259,8 +257,7 @@
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block
and rely on the dma controller to split it up if need be
- out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
- dma_select_low_bit,
dma_select_num_bits));
+ out_msg.Destination.add(TBEs[address].DmaRequestor);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
@@ -271,8 +268,7 @@
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:ACK;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
- dma_select_low_bit,
dma_select_num_bits));
+ out_msg.Destination.add(TBEs[address].DmaRequestor);
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@@ -343,6 +339,14 @@
TBEs[address].DataBlk := in_msg.DataBlk;
TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
TBEs[address].Len := in_msg.Len;
+ TBEs[address].DmaRequestor := in_msg.Requestor;
+ }
+ }
+
+ action(r_allocateTbeForDmaRead, "\r", desc="Allocate TBE for DMA Read") {
+ peek(dmaRequestQueue_in, DMARequestMsg) {
+ TBEs.allocate(address);
+ TBEs[address].DmaRequestor := in_msg.Requestor;
}
}
@@ -485,6 +489,7 @@
transition(I, DMA_READ, ID) {
//dr_sendDMAData;
+ r_allocateTbeForDmaRead;
qf_queueMemoryFetchRequestDMA;
p_popIncomingDMARequestQueue;
}
@@ -492,6 +497,7 @@
transition(ID, Memory_Data, I) {
dr_sendDMAData;
//p_popIncomingDMARequestQueue;
+ w_deallocateTBE;
l_popMemQueue;
}
diff -r 62c628499cd4 -r 554d84a850d6 src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/protocol/MI_example-dma.sm Wed Nov 18 13:55:58 2009 -0800
@@ -71,6 +71,7 @@
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
+ out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
out_msg.Destination.add(map_Address_to_Directory(address));
@@ -85,6 +86,7 @@
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:WRITE;
+ out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
out_msg.Destination.add(map_Address_to_Directory(address));
diff -r 62c628499cd4 -r 554d84a850d6 src/mem/protocol/MI_example-msg.sm
--- a/src/mem/protocol/MI_example-msg.sm Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/protocol/MI_example-msg.sm Wed Nov 18 13:55:58 2009 -0800
@@ -105,6 +105,7 @@
DMARequestType Type, desc="Request type (read/write)";
Address PhysicalAddress, desc="Physical address for this request";
Address LineAddress, desc="Line address for this request";
+ MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
int Len, desc="The length of the request";
diff -r 62c628499cd4 -r 554d84a850d6 src/mem/ruby/config/MI_example.rb
--- a/src/mem/ruby/config/MI_example.rb Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/ruby/config/MI_example.rb Wed Nov 18 13:55:58 2009 -0800
@@ -23,8 +23,6 @@
def argv()
vec = super()
vec += " directory_latency "+directory_latency.to_s
- vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
- vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
end
end
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
