changeset 2980bd04e6df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2980bd04e6df
description:
util: do checkpoint aggregation more cleanly, fix last changeset.
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an
function to do optional paramIn so that old checkpoints don't need to be fixed
up.
3) Fix up alpha startup code so that the unserialized M5_pid value is
properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last
changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench
foo-bar plus positional arguments foo bar are the only changes in usage from
se.py.
Note this aggregation stuff has only been tested for Alpha and nothing
else, though it should take a very minimal amount of work to get it to work
with another ISA.
diffstat:
7 files changed, 35 insertions(+), 20 deletions(-)
src/arch/alpha/process.cc | 9 +++++----
src/mem/page_table.cc | 10 ----------
src/mem/physical.cc | 8 ++------
src/sim/process.cc | 6 ++++++
src/sim/serialize.cc | 15 +++++++++++++++
src/sim/serialize.hh | 5 +++++
util/checkpoint-aggregator.py | 2 ++
diffs (156 lines):
diff -r a9c220194f14 -r 2980bd04e6df src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Mon Jan 18 14:33:02 2010 -0800
+++ b/src/arch/alpha/process.cc Tue Jan 19 22:03:44 2010 -0800
@@ -175,21 +175,22 @@
void
AlphaLiveProcess::startup()
{
- if (checkpointRestored)
+ ThreadContext *tc = system->getThreadContext(contextIds[0]);
+ tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
+
+ if (checkpointRestored) {
return;
+ }
Process::startup();
argsInit(MachineBytes, VMPageSize);
- ThreadContext *tc = system->getThreadContext(contextIds[0]);
tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
//Operate in user mode
tc->setMiscRegNoEffect(IPR_ICM, 0x18);
//No super page mapping
tc->setMiscRegNoEffect(IPR_MCSR, 0);
- //Set this to 0 for now, but it should be unique for each process
- tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
}
AlphaISA::IntReg
diff -r a9c220194f14 -r 2980bd04e6df src/mem/page_table.cc
--- a/src/mem/page_table.cc Mon Jan 18 14:33:02 2010 -0800
+++ b/src/mem/page_table.cc Tue Jan 19 22:03:44 2010 -0800
@@ -223,15 +223,5 @@
pTable[vaddr] = *entry;
++i;
}
-
- process->M5_pid = pTable[vaddr].asn;
-
-#if THE_ISA == ALPHA_ISA
- // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work
- // correctly
- int id = process->contextIds[0];
- ThreadContext *tc = process->system->getThreadContext(id);
- tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57);
-#endif
}
diff -r a9c220194f14 -r 2980bd04e6df src/mem/physical.cc
--- a/src/mem/physical.cc Mon Jan 18 14:33:02 2010 -0800
+++ b/src/mem/physical.cc Tue Jan 19 22:03:44 2010 -0800
@@ -540,12 +540,8 @@
/* Only copy bytes that are non-zero, so we don't give the VM system hell
*/
while (curSize < params()->range.size()) {
bytesRead = gzread(compressedMem, tempPage, chunkSize);
- if (bytesRead != chunkSize &&
- bytesRead != params()->range.size() - curSize)
- fatal("Read failed on physical memory checkpoint file '%s'"
- " got %d bytes, expected %d or %d bytes\n",
- filename, bytesRead, chunkSize,
- params()->range.size() - curSize);
+ if (bytesRead == 0)
+ break;
assert(bytesRead % sizeof(long) == 0);
diff -r a9c220194f14 -r 2980bd04e6df src/sim/process.cc
--- a/src/sim/process.cc Mon Jan 18 14:33:02 2010 -0800
+++ b/src/sim/process.cc Tue Jan 19 22:03:44 2010 -0800
@@ -507,6 +507,7 @@
nameOut(os, csprintf("%s.FdMap%d", name(), x));
fd_map[x].serialize(os);
}
+ SERIALIZE_SCALAR(M5_pid);
}
@@ -528,6 +529,11 @@
fd_map[x].unserialize(cp, csprintf("%s.FdMap%d", section, x));
}
fix_file_offsets();
+ UNSERIALIZE_OPT_SCALAR(M5_pid);
+ // The above returns a bool so that you could do something if you don't
+ // find the param in the checkpoint if you wanted to, like set a default
+ // but in this case we'll just stick with the instantianted value if not
+ // found.
checkpointRestored = true;
diff -r a9c220194f14 -r 2980bd04e6df src/sim/serialize.cc
--- a/src/sim/serialize.cc Mon Jan 18 14:33:02 2010 -0800
+++ b/src/sim/serialize.cc Tue Jan 19 22:03:44 2010 -0800
@@ -204,6 +204,18 @@
}
}
+template <class T>
+bool
+optParamIn(Checkpoint *cp, const string §ion, const string &name, T ¶m)
+{
+ string str;
+ if (!cp->find(section, name, str) || !parseParam(str, param)) {
+ warn("optional parameter %s:%s not present\n", section, name);
+ return false;
+ } else {
+ return true;
+ }
+}
template <class T>
void
@@ -322,6 +334,9 @@
template void \
paramIn(Checkpoint *cp, const string §ion, \
const string &name, type & param); \
+template bool \
+optParamIn(Checkpoint *cp, const string §ion, \
+ const string &name, type & param); \
template void \
arrayParamOut(ostream &os, const string &name, \
type const *param, unsigned size); \
diff -r a9c220194f14 -r 2980bd04e6df src/sim/serialize.hh
--- a/src/sim/serialize.hh Mon Jan 18 14:33:02 2010 -0800
+++ b/src/sim/serialize.hh Tue Jan 19 22:03:44 2010 -0800
@@ -58,6 +58,10 @@
const std::string &name, T ¶m);
template <class T>
+bool optParamIn(Checkpoint *cp, const std::string §ion,
+ const std::string &name, T ¶m);
+
+template <class T>
void arrayParamOut(std::ostream &os, const std::string &name,
const T *param, unsigned size);
@@ -85,6 +89,7 @@
#define SERIALIZE_SCALAR(scalar) paramOut(os, #scalar, scalar)
#define UNSERIALIZE_SCALAR(scalar) paramIn(cp, section, #scalar, scalar)
+#define UNSERIALIZE_OPT_SCALAR(scalar) optParamIn(cp, section, #scalar,
scalar)
// ENUMs are like SCALARs, but we cast them to ints on the way out
#define SERIALIZE_ENUM(scalar) paramOut(os, #scalar, (int)scalar)
diff -r a9c220194f14 -r 2980bd04e6df util/checkpoint-aggregator.py
--- a/util/checkpoint-aggregator.py Mon Jan 18 14:33:02 2010 -0800
+++ b/util/checkpoint-aggregator.py Tue Jan 19 22:03:44 2010 -0800
@@ -50,6 +50,8 @@
if re.compile("cpu").search(sec):
newsec = re.sub("cpu", "cpu" + str(i), sec)
merged.add_section(newsec)
+ if re.compile("workload$").search(sec):
+ merged.set(newsec, "M5_pid", i)
items = config.items(sec)
for item in items:
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