To follow up on this, I'm using the CPU frequency divided by 16 as the
bus frequency used by the local APIC. If anybody thinks that's
unreasonable let me know.
Gabe
Steve Reinhardt wrote:
On Thu, May 22, 2008 at 11:45 AM, Gabe Black [EMAIL PROTECTED]
mailto:[EMAIL PROTECTED] wrote:
For now, I'm going to make the miscregfile have the event and cause an
interrupt when the timer goes off. This really sounds crappy to me, but
I'd have to add new functions to get at the interrupt object like there
are for the TLB. That wouldn't be hard, but I wanted to point out I'd be
adding
Oh, and one thing I forgot, registers can be like faults where they're
little islands of the ISA. They know how to translate indexes, and they
could use bitunions, which if it works (I don't remember if it does)
could be inherited from (or inherit, with some modifications) to be able
to pull
Thanks for the email... can't say I really follow all the nuances
after a quick read, but I'm glad you're thinking about it. Just a few
comments off the top of my head:
The common indexing scheme across all register types is something we
inherited from SimpleScalar. It's not ideal for actually
On Wed, May 21, 2008 at 5:44 PM, Gabe Black [EMAIL PROTECTED] wrote:
The kernel is now getting to a point where it's trying to calibrate the
timer in the local APIC against the TSC register. In order to mimic that,
I'm going to need to create an event to fire when the timer is supposed to
One problem is that this isn't a parent/child relationship. For
instance, there could be four CPUs and four local APICs all on the same
bus, and they need to know which one goes with which CPU. In that case
it would be arbitrary. If the interconnect isn't a bus, then you can't
just stick the
