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This looks great. Thanks!
- Gabe
On 2010-07-20 17:05:54, Tushar Krishna
so base_dyn_inst is always used timing memory - I assumed so but just wanted
to confirm this to make sure that read function,
BaseDynInstImpl::read(Addr addr, T data, unsigned flags)
'data' argument isn't really doing anything but being a placeholder for func
sig matching in xc interface. -- is
changeset a75564db03c3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a75564db03c3
description:
Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses
diffstat:
src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py | 16 ++--
1 files
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Review request for Default.
Summary
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Power: The condition register should
On 2010-07-21 12:35:38, Ali Saidi wrote:
src/arch/power/process.cc, line 289
http://reviews.m5sim.org/r/62/diff/1/?file=815#file815line289
Can this be a const or something as apposed to magical bit 28?
Yes, no problem, I'll see what I can do.
- Timothy
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Ship it!
I'm happy.
- Ali
On 2010-07-21 13:14:02, Timothy Jones wrote:
Hello,
I have been playing with time in m5 syscall emulation mode and had a couple of
issues:
First of all I believe there is a bug in the times() syscall implementation
(sim/syscall_emul.hh). The current clocks value passed to the userland is:
int64_t clocks = curTick *
changeset ad631c296c9b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ad631c296c9b
description:
stats: cleanup a few small problems in stats
diffstat:
src/base/statistics.hh | 43 ---
src/base/stats/text.cc | 16
changeset 7772a8bf76ee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7772a8bf76ee
description:
stats: unify the two stats distribution type better
diffstat:
src/base/statistics.hh | 34 ++
src/base/stats/info.hh | 31
