[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
* build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest passed. * build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic passed. * build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby passed. * build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing passed. * build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing passed. * build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic passed. * build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing passed. * build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp passed. * build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp passed. * build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp passed. * build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby passed. *
[gem5-dev] changeset in m5: O3: Fix issue with interrupts/faults occuring i...
changeset 13ac7b9939ef in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=13ac7b9939ef
description:
O3: Fix issue with interrupts/faults occuring in the middle of a
macro-op
This patch fixes two problems with the O3 cpu model. The first is an
issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to
issue
if the next line faults a fault is attached to a micro-op in the
currently
executing macro-op rather than a nop from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.
A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is
incorrect
in the case of a macro-op as the current location might not be
interruptable.
diffstat:
src/arch/arm/faults.cc | 2 ++
src/cpu/o3/fetch.hh | 3 +++
src/cpu/o3/fetch_impl.hh | 28 +---
3 files changed, 26 insertions(+), 7 deletions(-)
diffs (98 lines):
diff -r 1eaa1fbd2212 -r 13ac7b9939ef src/arch/arm/faults.cc
--- a/src/arch/arm/faults.ccSat May 21 00:40:57 2011 -0400
+++ b/src/arch/arm/faults.ccMon May 23 10:40:18 2011 -0500
@@ -219,6 +219,8 @@
fsr.ext = 0;
tc-setMiscReg(T::FsrIndex, fsr);
tc-setMiscReg(T::FarIndex, faultAddr);
+
+DPRINTF(Faults, Abort Fault fsr=%#x faultAddr=%#x\n, fsr, faultAddr);
}
void
diff -r 1eaa1fbd2212 -r 13ac7b9939ef src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Sat May 21 00:40:57 2011 -0400
+++ b/src/cpu/o3/fetch.hh Mon May 23 10:40:18 2011 -0500
@@ -403,6 +403,9 @@
StaticInstPtr macroop[Impl::MaxThreads];
+/** Can the fetch stage redirect from an interrupt on this instruction? */
+bool delayedCommit[Impl::MaxThreads];
+
/** Memory request used to access cache. */
RequestPtr memReq[Impl::MaxThreads];
diff -r 1eaa1fbd2212 -r 13ac7b9939ef src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sat May 21 00:40:57 2011 -0400
+++ b/src/cpu/o3/fetch_impl.hh Mon May 23 10:40:18 2011 -0500
@@ -346,6 +346,7 @@
pc[tid] = cpu-pcState(tid);
fetchOffset[tid] = 0;
macroop[tid] = NULL;
+delayedCommit[tid] = false;
}
for (ThreadID tid = 0; tid numThreads; tid++) {
@@ -1070,6 +1071,9 @@
assert(numInst fetchWidth);
toDecode-insts[toDecode-size++] = instruction;
+// Keep track of if we can take an interrupt at this boundary
+delayedCommit[tid] = instruction-isDelayedCommit();
+
return instruction;
}
@@ -1112,8 +1116,11 @@
// Align the fetch PC so its at the start of a cache block.
Addr block_PC = icacheBlockAlignPC(fetchAddr);
-// Unless buffer already got the block, fetch it from icache.
-if (!(cacheDataValid[tid] block_PC == cacheDataPC[tid]) !inRom) {
+// If buffer is no longer valid or fetchAddr has moved to point
+// to the next cache block, AND we have no remaining ucode
+// from a macro-op, then start fetch from icache.
+if (!(cacheDataValid[tid] block_PC == cacheDataPC[tid])
+ !inRom !macroop[tid]) {
DPRINTF(Fetch, [tid:%i]: Attempting to translate and read
instruction, starting at PC %s.\n, tid, thisPC);
@@ -1126,7 +1133,11 @@
else
++fetchMiscStallCycles;
return;
-} else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) {
+} else if ((checkInterrupt(thisPC.instAddr()) !delayedCommit[tid])
+ || isSwitchedOut()) {
+// Stall CPU if an interrupt is posted and we're not issuing
+// an delayed commit micro-op currently (delayed commit
instructions
+// are not interruptable by interrupts, only faults)
++fetchMiscStallCycles;
return;
}
@@ -1184,9 +1195,11 @@
unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
// Loop through instruction memory from the cache.
-while (blkOffset numInsts
- numInst fetchWidth
- !predictedBranch) {
+// Keep issuing while we have not reached the end of the block or a
+// macroop is active and fetchWidth is available and branch is not
+// predicted taken
+while ((blkOffset numInsts || curMacroop)
+ numInst fetchWidth !predictedBranch) {
// If we need to process more memory, do it now.
if (!(curMacroop || inRom) !predecoder.extMachInstReady()) {
@@ -1232,7 +1245,8 @@
pcOffset = 0;
}
}
[gem5-dev] changeset in m5: O3: Fix issue w/wbOutstading being decremented ...
changeset 6173b87e7652 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6173b87e7652
description:
O3: Fix issue w/wbOutstading being decremented multiple times on
blocked cache.
If a split load fails on a blocked cache wbOutstanding can be
decremented
twice if the first part of the split load succeeds and the second part
fails.
Condition the decrementing on not having completed the first part of
the load.
diffstat:
src/cpu/o3/iew.hh | 2 +-
src/cpu/o3/iew_impl.hh | 4 +++-
src/cpu/o3/lsq_unit.hh | 7 ++-
3 files changed, 10 insertions(+), 3 deletions(-)
diffs (43 lines):
diff -r 13ac7b9939ef -r 6173b87e7652 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Mon May 23 10:40:18 2011 -0500
+++ b/src/cpu/o3/iew.hh Mon May 23 10:40:19 2011 -0500
@@ -228,7 +228,7 @@
{
if (++wbOutstanding == wbMax)
ableToIssue = false;
-DPRINTF(IEW, wbOutstanding: %i\n, wbOutstanding);
+DPRINTF(IEW, wbOutstanding: %i [sn:%lli]\n, wbOutstanding, sn);
assert(wbOutstanding = wbMax);
#ifdef DEBUG
wbList.insert(sn);
diff -r 13ac7b9939ef -r 6173b87e7652 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hhMon May 23 10:40:18 2011 -0500
+++ b/src/cpu/o3/iew_impl.hhMon May 23 10:40:19 2011 -0500
@@ -1221,7 +1221,9 @@
// Check if the instruction is squashed; if so then skip it
if (inst-isSquashed()) {
-DPRINTF(IEW, Execute: Instruction was squashed.\n);
+DPRINTF(IEW, Execute: Instruction was squashed. PC: %s, [tid:%i]
+ [sn:%i]\n, inst-pcState(), inst-threadNumber,
+ inst-seqNum);
// Consider this instruction executed so that commit can go
// ahead and retire the instruction.
diff -r 13ac7b9939ef -r 6173b87e7652 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hhMon May 23 10:40:18 2011 -0500
+++ b/src/cpu/o3/lsq_unit.hhMon May 23 10:40:19 2011 -0500
@@ -804,7 +804,12 @@
++lsqCacheBlocked;
-iewStage-decrWb(load_inst-seqNum);
+// If the first part of a split access succeeds, then let the LSQ
+// handle the decrWb when completeDataAccess is called upon return
+// of the requested first part of data
+if (!completedFirst)
+iewStage-decrWb(load_inst-seqNum);
+
// There's an older load that's already going to squash.
if (isLoadBlocked blockedLoadSeqNum load_inst-seqNum)
return NoFault;
___
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[gem5-dev] changeset in m5: Stats: Update stats for minor O3 changes below.
changeset 7f106d0bd638 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7f106d0bd638 description: Stats: Update stats for minor O3 changes below. diffstat: tests/long/00.gzip/ref/arm/linux/o3-timing/simout| 8 +- tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1006 +++--- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |10 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 848 +++--- tests/long/00.gzip/ref/x86/linux/o3-timing/simout|10 +- tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 830 ++-- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr| 2 - tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout| 8 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1390 +- tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 8 +- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 952 +++--- tests/long/10.mcf/ref/x86/linux/o3-timing/simout |10 +- tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 840 +++--- tests/long/20.parser/ref/arm/linux/o3-timing/simout | 8 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 1016 +++--- tests/long/20.parser/ref/x86/linux/o3-timing/simout |18 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 888 +++--- tests/long/30.eon/ref/arm/linux/o3-timing/simout | 8 +- tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt | 963 +++--- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 8 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1008 +++--- tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 8 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1013 +++--- tests/long/60.bzip2/ref/arm/linux/o3-timing/simout | 8 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt| 948 +++--- tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 8 +- tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt| 980 +++--- tests/long/70.twolf/ref/x86/linux/o3-timing/simout |10 +- tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt| 877 +++--- tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 8 +- tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 964 +++--- tests/quick/00.hello/ref/x86/linux/o3-timing/simout |10 +- tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 808 ++-- 33 files changed, 7753 insertions(+), 7728 deletions(-) diffs (truncated from 16305 to 300 lines): diff -r 6fd588813142 -r 7f106d0bd638 tests/long/00.gzip/ref/arm/linux/o3-timing/simout --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Mon May 23 10:40:21 2011 -0500 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Mon May 23 10:59:13 2011 -0500 @@ -7,9 +7,9 @@ All Rights Reserved -M5 compiled May 4 2011 13:56:47 -M5 started May 4 2011 13:57:03 -M5 executing on nadc-0364 +M5 compiled May 16 2011 15:11:25 +M5 started May 16 2011 16:32:58 +M5 executing on nadc-0271 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 18974767 because target called exit() +Exiting @ tick 18974525 because target called exit() diff -r 6fd588813142 -r 7f106d0bd638 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Mon May 23 10:40:21 2011 -0500 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Mon May 23 10:59:13 2011 -0500 @@ -1,530 +1,530 @@ -- Begin Simulation Statistics -- -host_inst_rate 210962 # Simulator instruction rate (inst/s) -host_mem_usage 262196 # Number of bytes of host memory used -host_seconds 2855.31 # Real time elapsed on the host -host_tick_rate 66454392 # Simulator tick rate (ticks/s) +sim_seconds 0.189745 # Number of seconds simulated +sim_ticks18974525 # Number of ticks simulated sim_freq 1 # Frequency of simulated ticks -sim_insts 602359850 # Number of
[gem5-dev] Review Request: config: tweak ruby configs to clean up hierarchy
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/709/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- config: tweak ruby configs to clean up hierarchy Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. [Note: the previous patch referred to above is http://reviews.m5sim.org/r/608 , which will be the previous patch when I commit these.] Diffs - configs/example/ruby_direct_test.py 7f106d0bd638 configs/example/ruby_fs.py 7f106d0bd638 configs/example/ruby_mem_test.py 7f106d0bd638 configs/example/ruby_network_test.py 7f106d0bd638 configs/example/ruby_random_test.py 7f106d0bd638 configs/example/se.py 7f106d0bd638 configs/ruby/MESI_CMP_directory.py 7f106d0bd638 configs/ruby/MI_example.py 7f106d0bd638 configs/ruby/MOESI_CMP_directory.py 7f106d0bd638 configs/ruby/MOESI_CMP_token.py 7f106d0bd638 configs/ruby/MOESI_hammer.py 7f106d0bd638 configs/ruby/Ruby.py 7f106d0bd638 src/mem/ruby/network/topologies/Crossbar.py 7f106d0bd638 src/mem/ruby/network/topologies/Mesh.py 7f106d0bd638 src/mem/ruby/network/topologies/MeshDirCorners.py 7f106d0bd638 src/mem/ruby/network/topologies/Pt2Pt.py 7f106d0bd638 src/mem/ruby/network/topologies/Torus.py 7f106d0bd638 tests/configs/memtest-ruby.py 7f106d0bd638 tests/configs/rubytest-ruby.py 7f106d0bd638 tests/configs/simple-timing-mp-ruby.py 7f106d0bd638 tests/configs/simple-timing-ruby.py 7f106d0bd638 Diff: http://reviews.m5sim.org/r/709/diff Testing --- Thanks, Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Auto-generated error/warning URLs
You know the For more information see: http://www.m5sim.org/warn/3a2134f6; URLs? How many of these are actually used? They seem mostly like noise to me. If we're not using them, can we get rid of them? Seems like it's just as intuitive to search for the warning/error string on the wiki (or in the mailing list). Thoughts? Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request: config: tweak ruby configs to clean up hierarchy
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/709/#review1253 --- Hi Steve, I think you will also have to make similar changes in configs/ruby/Network_test.py -Tushar - Tushar On 2011-05-23 09:23:34, Steve Reinhardt wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/709/ --- (Updated 2011-05-23 09:23:34) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- config: tweak ruby configs to clean up hierarchy Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. [Note: the previous patch referred to above is http://reviews.m5sim.org/r/608 , which will be the previous patch when I commit these.] Diffs - configs/example/ruby_direct_test.py 7f106d0bd638 configs/example/ruby_fs.py 7f106d0bd638 configs/example/ruby_mem_test.py 7f106d0bd638 configs/example/ruby_network_test.py 7f106d0bd638 configs/example/ruby_random_test.py 7f106d0bd638 configs/example/se.py 7f106d0bd638 configs/ruby/MESI_CMP_directory.py 7f106d0bd638 configs/ruby/MI_example.py 7f106d0bd638 configs/ruby/MOESI_CMP_directory.py 7f106d0bd638 configs/ruby/MOESI_CMP_token.py 7f106d0bd638 configs/ruby/MOESI_hammer.py 7f106d0bd638 configs/ruby/Ruby.py 7f106d0bd638 src/mem/ruby/network/topologies/Crossbar.py 7f106d0bd638 src/mem/ruby/network/topologies/Mesh.py 7f106d0bd638 src/mem/ruby/network/topologies/MeshDirCorners.py 7f106d0bd638 src/mem/ruby/network/topologies/Pt2Pt.py 7f106d0bd638 src/mem/ruby/network/topologies/Torus.py 7f106d0bd638 tests/configs/memtest-ruby.py 7f106d0bd638 tests/configs/rubytest-ruby.py 7f106d0bd638 tests/configs/simple-timing-mp-ruby.py 7f106d0bd638 tests/configs/simple-timing-ruby.py 7f106d0bd638 Diff: http://reviews.m5sim.org/r/709/diff Testing --- Thanks, Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Auto-generated error/warning URLs
According to this: http://m5sim.org/Special:AllPages only one exists created by Ali last August. I'm all for getting rid of those links and I think I've even suggested it a time or two in the past. Gabe Quoting Steve Reinhardt ste...@gmail.com: You know the For more information see: http://www.m5sim.org/warn/3a2134f6; URLs? How many of these are actually used? They seem mostly like noise to me. If we're not using them, can we get rid of them? Seems like it's just as intuitive to search for the warning/error string on the wiki (or in the mailing list). Thoughts? Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request: syscall emul: fix Power Linux mmap constant, plus other cleanup
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/710/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- syscall emul: fix Power Linux mmap constant, plus other cleanup We were getting a spurious warning in the regressions that turned out to be due to having the wrong value for TGT_MAP_ANONYMOUS for Power Linux, but in the process of tracking it down I ended up doing some cleanup of the mmap handling in general. Diffs - src/arch/power/linux/linux.hh 3f37cc5d25bc src/sim/process.cc 3f37cc5d25bc src/sim/syscall_emul.hh 3f37cc5d25bc Diff: http://reviews.m5sim.org/r/710/diff Testing --- Thanks, Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Auto-generated error/warning URLs
That is fine with me.. It was one of those good ideas at the time that didn't make it. Ali On May 23, 2011, at 1:29 PM, Gabriel Michael Black wrote: According to this: http://m5sim.org/Special:AllPages only one exists created by Ali last August. I'm all for getting rid of those links and I think I've even suggested it a time or two in the past. Gabe Quoting Steve Reinhardt ste...@gmail.com: You know the For more information see: http://www.m5sim.org/warn/3a2134f6; URLs? How many of these are actually used? They seem mostly like noise to me. If we're not using them, can we get rid of them? Seems like it's just as intuitive to search for the warning/error string on the wiki (or in the mailing list). Thoughts? Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request: syscall emul: fix Power Linux mmap constant, plus other cleanup
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/710/#review1255 --- Ship it! - Ali On 2011-05-23 16:48:45, Steve Reinhardt wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/710/ --- (Updated 2011-05-23 16:48:45) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- syscall emul: fix Power Linux mmap constant, plus other cleanup We were getting a spurious warning in the regressions that turned out to be due to having the wrong value for TGT_MAP_ANONYMOUS for Power Linux, but in the process of tracking it down I ended up doing some cleanup of the mmap handling in general. Diffs - src/arch/power/linux/linux.hh 3f37cc5d25bc src/sim/process.cc 3f37cc5d25bc src/sim/syscall_emul.hh 3f37cc5d25bc Diff: http://reviews.m5sim.org/r/710/diff Testing --- Thanks, Steve ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request: garnet: add network ptr to links
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/711/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan Binkert, and Brad Beckmann. Summary --- garnet: added network ptr to links to be used by orion Diffs - src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 3f37cc5d25bc src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh 3f37cc5d25bc src/mem/ruby/network/orion/NetworkPower.cc 3f37cc5d25bc Diff: http://reviews.m5sim.org/r/711/diff Testing --- Thanks, Tushar ___ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in m5: util/regress: make default action a more thorou...
changeset 6a49ac49fd67 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6a49ac49fd67
description:
util/regress: make default action a more thorough regression
Changed the --variants option to --test-variants and added a new
--compile-variants option for variants that are only compiled
(not tested). The former still defaults to 'opt' and the latter
defaults to 'debug,fast'.
Also changed the behavior when no tests are specified from just
compiling to running the 'quick' tests.
As a result, a plain 'util/regress' invocation will now compile
(but not test) the debug and fast builds, and compile and run the
quick regressions on the opt build. This should be the default
set of tests that are run before committing. Since the nightly
regressions use this same script, this will also be the new
nightly regression behavior.
Test-only regressions can still be done by setting --compile=''.
Compile-only regressions can be done by setting --test=''.
diffstat:
util/regress | 78 ---
1 files changed, 48 insertions(+), 30 deletions(-)
diffs (126 lines):
diff -r 3f37cc5d25bc -r 6a49ac49fd67 util/regress
--- a/util/regress Mon May 23 14:36:22 2011 -0400
+++ b/util/regress Mon May 23 14:27:20 2011 -0700
@@ -37,10 +37,9 @@
optparser = optparse.OptionParser()
add_option = optparser.add_option
-add_option('-v', '--verbose', dest='verbose', action='store_true',
- default=False,
+add_option('-v', '--verbose', action='store_true', default=False,
help='echo commands before executing')
-add_option('--builds', dest='builds',
+add_option('--builds',
default='ALPHA_SE,ALPHA_SE_MOESI_hammer,' \
'ALPHA_SE_MESI_CMP_directory,' \
'ALPHA_SE_MOESI_CMP_directory,' \
@@ -52,15 +51,21 @@
'X86_SE,X86_FS,' \
'ARM_SE,ARM_FS',
help=comma-separated build targets to test (default: '%default'))
-add_option('--variants', dest='variants', default='opt',
- help=comma-separated build variants to test (default: '%default'))
-add_option('--scons-opts', dest='scons_opts', default='', metavar='OPTS',
+add_option('--test-variants', default='opt',
+ help=comma-separated build variants to test (default: '%default')\
+ , set to '' for none)
+add_option('--compile-variants', default='debug,fast',
+ help=comma-separated build variants to compile only (not test) \
+ (default: '%default'), set to '' for none, metavar='VARIANTS')
+add_option('--scons-opts', default='', metavar='OPTS',
help='scons options')
-add_option('-j', '--jobs', type='int', default=1,
- help='number of parallel jobs to use')
+add_option('-j', '--jobs', type='int', default=1, metavar='N',
+ help='number of parallel jobs to use (0 to use all cores)')
add_option('-k', '--keep-going', action='store_true',
help='keep going after errors')
-add_option('-D', '--build-dir', default='',
+add_option('--update-ref', action='store_true',
+ help='update reference outputs')
+add_option('-D', '--build-dir', default='', metavar='DIR',
help='build directory location')
add_option('-n', --no-exec, default=False, action='store_true',
help=don't actually invoke scons, just echo SCons command line)
@@ -68,9 +73,17 @@
(options, tests) = optparser.parse_args()
+# split a comma-separated list, but return an empty list if given the
+# empty string
+def split_if_nonempty(s):
+if not s:
+return []
+return s.split(',')
+
# split list options on ',' to get Python lists
-builds = options.builds.split(',')
-variants = options.variants.split(',')
+builds = split_if_nonempty(options.builds)
+test_variants = split_if_nonempty(options.test_variants)
+compile_variants = split_if_nonempty(options.compile_variants)
options.build_dir = os.path.join(options.build_dir, 'build')
@@ -91,30 +104,33 @@
print sys.stderr, When attemping to execute: %s % cmd
sys.exit(1)
-# Quote string s so it can be passed as a shell arg
-def shellquote(s):
-if ' ' in s:
-s = '%s' % s
-return s
+targets = []
+# start with compile-only targets, if any
+if compile_variants:
+targets += ['%s/%s/m5.%s' % (options.build_dir, build, variant)
+for variant in compile_variants
+for build in builds]
+
+# By default run the 'quick' tests
if not tests:
-print No tests specified, just building binaries.
-targets = ['%s/%s/m5.%s' % (options.build_dir, build, variant)
- for build in builds
- for variant in variants]
-elif 'all' in tests:
-targets = ['%s/%s/tests/%s' % (options.build_dir, build, variant)
- for build in builds
- for variant in variants]
+tests =
[gem5-dev] changeset in m5: sim: add some DPRINTFs for debugging unserializ...
changeset c03e683e83fe in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c03e683e83fe
description:
sim: add some DPRINTFs for debugging unserialization
Also got rid of unused C++ unserializeAll() method
(this is now handled in Python)
diffstat:
src/sim/sim_object.cc | 27 ++-
src/sim/sim_object.hh | 1 -
2 files changed, 6 insertions(+), 22 deletions(-)
diffs (63 lines):
diff -r 6a49ac49fd67 -r c03e683e83fe src/sim/sim_object.cc
--- a/src/sim/sim_object.cc Mon May 23 14:27:20 2011 -0700
+++ b/src/sim/sim_object.cc Mon May 23 14:27:20 2011 -0700
@@ -38,7 +38,7 @@
#include base/misc.hh
#include base/trace.hh
#include base/types.hh
-#include debug/Config.hh
+#include debug/Checkpoint.hh
#include sim/sim_object.hh
#include sim/stats.hh
@@ -78,8 +78,12 @@
void
SimObject::loadState(Checkpoint *cp)
{
-if (cp-sectionExists(name()))
+if (cp-sectionExists(name())) {
+DPRINTF(Checkpoint, unserializing\n);
unserialize(cp, name());
+} else {
+DPRINTF(Checkpoint, no checkpoint section found\n);
+}
}
void
@@ -126,25 +130,6 @@
}
}
-void
-SimObject::unserializeAll(Checkpoint *cp)
-{
-SimObjectList::reverse_iterator ri = simObjectList.rbegin();
-SimObjectList::reverse_iterator rend = simObjectList.rend();
-
-for (; ri != rend; ++ri) {
-SimObject *obj = *ri;
-DPRINTFR(Config, Unserializing '%s'\n,
- obj-name());
-if(cp-sectionExists(obj-name()))
-obj-unserialize(cp, obj-name());
-else
-warn(Not unserializing '%s': no section found in checkpoint.\n,
- obj-name());
- }
-}
-
-
#ifdef DEBUG
//
diff -r 6a49ac49fd67 -r c03e683e83fe src/sim/sim_object.hh
--- a/src/sim/sim_object.hh Mon May 23 14:27:20 2011 -0700
+++ b/src/sim/sim_object.hh Mon May 23 14:27:20 2011 -0700
@@ -138,7 +138,6 @@
// static: call nameOut() serialize() on all SimObjects
static void serializeAll(std::ostream );
-static void unserializeAll(Checkpoint *cp);
// Methods to drain objects in order to take checkpoints
// Or switch from timing - atomic memory model
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[gem5-dev] changeset in m5: config: tweak ruby configs to clean up hierarchy
changeset 19949c6de823 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=19949c6de823 description: config: tweak ruby configs to clean up hierarchy Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. diffstat: configs/example/ruby_direct_test.py | 4 +- configs/example/ruby_fs.py| 8 +++--- configs/example/ruby_mem_test.py | 6 ++-- configs/example/ruby_network_test.py | 2 +- configs/example/ruby_random_test.py | 4 +- configs/example/se.py | 6 ++-- configs/ruby/MESI_CMP_directory.py| 15 ++- configs/ruby/MI_example.py| 11 --- configs/ruby/MOESI_CMP_directory.py | 15 ++- configs/ruby/MOESI_CMP_token.py | 21 --- configs/ruby/MOESI_hammer.py | 19 +++-- configs/ruby/Network_test.py | 11 --- configs/ruby/Ruby.py | 2 +- src/mem/ruby/network/topologies/Crossbar.py | 17 ++-- src/mem/ruby/network/topologies/Mesh.py | 25 +++--- src/mem/ruby/network/topologies/MeshDirCorners.py | 30 -- src/mem/ruby/network/topologies/Pt2Pt.py | 16 ++- src/mem/ruby/network/topologies/Torus.py | 24 ++--- tests/configs/memtest-ruby.py | 4 +- tests/configs/rubytest-ruby.py| 4 +- tests/configs/simple-timing-mp-ruby.py| 6 ++-- tests/configs/simple-timing-ruby.py | 6 ++-- 22 files changed, 138 insertions(+), 118 deletions(-) diffs (truncated from 676 to 300 lines): diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_direct_test.py --- a/configs/example/ruby_direct_test.py Mon May 23 14:29:08 2011 -0700 +++ b/configs/example/ruby_direct_test.py Mon May 23 14:29:23 2011 -0700 @@ -99,9 +99,9 @@ system.ruby = Ruby.create_system(options, system) -assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) +assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) -for ruby_port in system.ruby.cpu_ruby_ports: +for ruby_port in system.ruby._cpu_ruby_ports: # # Tie the ruby tester ports to the ruby cpu ports # diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_fs.py --- a/configs/example/ruby_fs.pyMon May 23 14:29:08 2011 -0700 +++ b/configs/example/ruby_fs.pyMon May 23 14:29:23 2011 -0700 @@ -128,11 +128,11 @@ # # Tie the cpu ports to the correct ruby system ports # -cpu.icache_port = system.ruby.cpu_ruby_ports[i].port -cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port +cpu.icache_port = system.ruby._cpu_ruby_ports[i].port +cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port if buildEnv['TARGET_ISA'] == x86: -cpu.itb.walker.port = system.ruby.cpu_ruby_ports[i].port -cpu.dtb.walker.port = system.ruby.cpu_ruby_ports[i].port +cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port +cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port cpu.interrupts.pio = system.piobus.port cpu.interrupts.int_port = system.piobus.port diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_mem_test.py --- a/configs/example/ruby_mem_test.py Mon May 23 14:29:08 2011 -0700 +++ b/configs/example/ruby_mem_test.py Mon May 23 14:29:23 2011 -0700 @@ -126,20 +126,20 @@ # system.ruby.randomization = True -assert(len(cpus) == len(system.ruby.cpu_ruby_ports)) +assert(len(cpus) ==
[gem5-dev] changeset in m5: config: revamp x86 config to avoid appending to...
changeset fd20dcf1a9aa in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=fd20dcf1a9aa description: config: revamp x86 config to avoid appending to SimObjectVectors A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams(). diffstat: configs/common/FSConfig.py | 40 +--- src/arch/x86/bios/E820.py | 2 +- src/dev/x86/SouthBridge.py | 29 ++--- 3 files changed, 32 insertions(+), 39 deletions(-) diffs (168 lines): diff -r 19949c6de823 -r fd20dcf1a9aa configs/common/FSConfig.py --- a/configs/common/FSConfig.pyMon May 23 14:29:23 2011 -0700 +++ b/configs/common/FSConfig.pyMon May 23 14:29:23 2011 -0700 @@ -306,7 +306,7 @@ def x86IOAddress(port): IO_address_space_base = 0x8000 -return IO_address_space_base + port; +return IO_address_space_base + port def connectX86ClassicSystem(x86_sys): x86_sys.membus = MemBus(bus_id=1) @@ -375,27 +375,29 @@ self.smbios_table.structures = structures # Set up the Intel MP table +base_entries = [] +ext_entries = [] for i in xrange(numCPUs): bp = X86IntelMPProcessor( local_apic_id = i, local_apic_version = 0x14, enable = True, bootstrap = (i == 0)) -self.intel_mp_table.add_entry(bp) +base_entries.append(bp) io_apic = X86IntelMPIOAPIC( id = numCPUs, version = 0x11, enable = True, address = 0xfec0) self.pc.south_bridge.io_apic.apic_id = io_apic.id -self.intel_mp_table.add_entry(io_apic) +base_entries.append(io_apic) isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') -self.intel_mp_table.add_entry(isa_bus) +base_entries.append(isa_bus) pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') -self.intel_mp_table.add_entry(pci_bus) +base_entries.append(pci_bus) connect_busses = X86IntelMPBusHierarchy(bus_id=0, subtractive_decode=True, parent_bus=1) -self.intel_mp_table.add_entry(connect_busses) +ext_entries.append(connect_busses) pci_dev4_inta = X86IntelMPIOIntAssignment( interrupt_type = 'INT', polarity = 'ConformPolarity', @@ -404,7 +406,7 @@ source_bus_irq = 0 + (4 2), dest_io_apic_id = io_apic.id, dest_io_apic_intin = 16) -self.intel_mp_table.add_entry(pci_dev4_inta); +base_entries.append(pci_dev4_inta) def assignISAInt(irq, apicPin): assign_8259_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'ExtInt', @@ -414,7 +416,7 @@ source_bus_irq = irq, dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) -self.intel_mp_table.add_entry(assign_8259_to_apic) +base_entries.append(assign_8259_to_apic) assign_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'INT', polarity = 'ConformPolarity', @@ -423,11 +425,13 @@ source_bus_irq = irq, dest_io_apic_id = io_apic.id, dest_io_apic_intin = apicPin) -self.intel_mp_table.add_entry(assign_to_apic) +base_entries.append(assign_to_apic) assignISAInt(0, 2) assignISAInt(1, 1) for i in range(3, 15): assignISAInt(i, i) +self.intel_mp_table.base_entries = base_entries +self.intel_mp_table.ext_entries = ext_entries def setWorkCountOptions(system, options): if options.work_item_id != None: @@ -456,17 +460,15 @@ # just to avoid corner cases. assert(self.physmem.range.second.getValue() = 0x20) -# Mark the first megabyte of memory as reserved -self.e820_table.entries.append(X86E820Entry( -addr = 0, -size = '1MB', -range_type = 2)) - -# Mark the rest as available -self.e820_table.entries.append(X86E820Entry( -addr = 0x10, +self.e820_table.entries = \ + [ +# Mark the first megabyte of memory as reserved +X86E820Entry(addr = 0, size = '1MB', range_type = 2), +# Mark the rest as
[gem5-dev] changeset in m5: syscall emul: fix Power Linux mmap constant, pl...
changeset aa7a67647c7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aa7a67647c7b
description:
syscall emul: fix Power Linux mmap constant, plus other cleanup
We were getting a spurious warning in the regressions that turned
out to be due to having the wrong value for TGT_MAP_ANONYMOUS for
Power Linux, but in the process of tracking it down I ended up
doing some cleanup of the mmap handling in general.
diffstat:
src/arch/power/linux/linux.hh | 2 +-
src/sim/process.cc| 6 +++---
src/sim/syscall_emul.hh | 31 ++-
3 files changed, 22 insertions(+), 17 deletions(-)
diffs (92 lines):
diff -r fd20dcf1a9aa -r aa7a67647c7b src/arch/power/linux/linux.hh
--- a/src/arch/power/linux/linux.hh Mon May 23 14:29:23 2011 -0700
+++ b/src/arch/power/linux/linux.hh Mon May 23 14:29:23 2011 -0700
@@ -126,7 +126,7 @@
//@}
/// For mmap().
-static const unsigned TGT_MAP_ANONYMOUS = 0x800;
+static const unsigned TGT_MAP_ANONYMOUS = 0x20;
//@{
/// ioctl() command codes.
diff -r fd20dcf1a9aa -r aa7a67647c7b src/sim/process.cc
--- a/src/sim/process.ccMon May 23 14:29:23 2011 -0700
+++ b/src/sim/process.ccMon May 23 14:29:23 2011 -0700
@@ -313,7 +313,7 @@
int
Process::sim_fd(int tgt_fd)
{
-if (tgt_fd MAX_FD)
+if (tgt_fd 0 || tgt_fd MAX_FD)
return -1;
return fd_map[tgt_fd].fd;
@@ -322,8 +322,8 @@
Process::FdMap *
Process::sim_fd_obj(int tgt_fd)
{
-if (tgt_fd MAX_FD)
-panic(sim_fd_obj called in fd out of range.);
+if (tgt_fd 0 || tgt_fd MAX_FD)
+return NULL;
return fd_map[tgt_fd];
}
diff -r fd20dcf1a9aa -r aa7a67647c7b src/sim/syscall_emul.hh
--- a/src/sim/syscall_emul.hh Mon May 23 14:29:23 2011 -0700
+++ b/src/sim/syscall_emul.hh Mon May 23 14:29:23 2011 -0700
@@ -989,13 +989,8 @@
/// We don't really handle mmap(). If the target is mmaping an
/// anonymous region or /dev/zero, we can get away with doing basically
/// nothing (since memory is initialized to zero and the simulator
-/// doesn't really check addresses anyway). Always print a warning,
-/// since this could be seriously broken if we're not mapping
-/// /dev/zero.
-//
-/// Someday we should explicitly check for /dev/zero in open, flag the
-/// file descriptor, and fail (or implement!) a non-anonymous mmap to
-/// anything else.
+/// doesn't really check addresses anyway).
+///
template class OS
SyscallReturn
mmapFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
@@ -1005,9 +1000,24 @@
uint64_t length = p-getSyscallArg(tc, index);
index++; // int prot = p-getSyscallArg(tc, index);
int flags = p-getSyscallArg(tc, index);
-int fd = p-sim_fd(p-getSyscallArg(tc, index));
+int tgt_fd = p-getSyscallArg(tc, index);
// int offset = p-getSyscallArg(tc, index);
+if (!(flags OS::TGT_MAP_ANONYMOUS)) {
+Process::FdMap *fd_map = p-sim_fd_obj(tgt_fd);
+if (!fd_map || fd_map-fd 0) {
+warn(mmap failing: target fd %d is not valid\n, tgt_fd);
+return -EBADF;
+}
+
+if (fd_map-filename != /dev/zero) {
+// This is very likely broken, but leave a warning here
+// (rather than panic) in case /dev/zero is known by
+// another name on some platform
+warn(allowing mmap of file %s; mmap not supported on files
+ other than /dev/zero\n, fd_map-filename);
+}
+}
if ((start % TheISA::VMPageSize) != 0 ||
(length % TheISA::VMPageSize) != 0) {
@@ -1032,11 +1042,6 @@
}
p-pTable-allocate(start, length);
-if (!(flags OS::TGT_MAP_ANONYMOUS)) {
-warn(allowing mmap of file @ fd %d.
- This will break if not /dev/zero., fd);
-}
-
return start;
}
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[gem5-dev] changeset in m5: sim: style fixes in sim/process.hh
changeset 76095b05f4da in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=76095b05f4da
description:
sim: style fixes in sim/process.hh
diffstat:
src/sim/process.hh | 46 +++---
1 files changed, 19 insertions(+), 27 deletions(-)
diffs (104 lines):
diff -r aa7a67647c7b -r 76095b05f4da src/sim/process.hh
--- a/src/sim/process.hhMon May 23 14:29:23 2011 -0700
+++ b/src/sim/process.hhMon May 23 14:29:23 2011 -0700
@@ -126,7 +126,7 @@
protected:
// constructor
-Process(ProcessParams * params);
+Process(ProcessParams *params);
virtual void initState();
@@ -144,30 +144,21 @@
class FdMap
{
public:
-int fd;
-std::string filename;
-int mode;
-int flags;
-bool isPipe;
-int readPipeSource;
-uint64_t fileOffset;
+int fd;
+std::string filename;
+int mode;
+int flags;
+bool isPipe;
+int readPipeSource;
+uint64_t fileOffset;
-
-FdMap()
-{
-fd = -1;
-filename = NULL;
-mode = 0;
-flags = 0;
-isPipe = false;
-readPipeSource = 0;
-fileOffset = 0;
-
-}
+FdMap()
+: fd(-1), filename(NULL), mode(0), flags(0),
+ isPipe(false), readPipeSource(0), fileOffset(0)
+{ }
void serialize(std::ostream os);
void unserialize(Checkpoint *cp, const std::string section);
-
};
private:
@@ -192,13 +183,14 @@
}
// Find a free context to use
-ThreadContext * findFreeContext();
+ThreadContext *findFreeContext();
// map simulator fd sim_fd to target fd tgt_fd
void dup_fd(int sim_fd, int tgt_fd);
// generate new target fd for sim_fd
-int alloc_fd(int sim_fd, std::string filename, int flags, int mode, bool
pipe);
+int alloc_fd(int sim_fd, std::string filename, int flags, int mode,
+ bool pipe);
// free target fd (e.g., after close)
void free_fd(int tgt_fd);
@@ -207,7 +199,7 @@
int sim_fd(int tgt_fd);
// look up simulator fd_map object for a given target fd
-FdMap * sim_fd_obj(int tgt_fd);
+FdMap *sim_fd_obj(int tgt_fd);
// fix all offsets for currently open files and save them
void fix_file_offsets();
@@ -240,7 +232,7 @@
std::vectorstd::string envp;
std::string cwd;
-LiveProcess(LiveProcessParams * params, ObjectFile *objFile);
+LiveProcess(LiveProcessParams *params, ObjectFile *objFile);
// Id of the owner of the process
uint64_t __uid;
@@ -316,12 +308,12 @@
virtual void setSyscallReturn(ThreadContext *tc,
SyscallReturn return_value) = 0;
-virtual SyscallDesc* getDesc(int callnum) = 0;
+virtual SyscallDesc *getDesc(int callnum) = 0;
// this function is used to create the LiveProcess object, since
// we can't tell which subclass of LiveProcess to use until we
// open and look at the object file.
-static LiveProcess *create(LiveProcessParams * params);
+static LiveProcess *create(LiveProcessParams *params);
};
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