changeset 3995b7c2ae86 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3995b7c2ae86
description:
X86: Panic when an unimplemented fault is invoked, rather than spinning
forever
diffstat:
1 file changed, 3 insertions(+)
src/arch/x86/faults.hh |3 +++
diffs (16
changeset a55b78e4b6d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a55b78e4b6d6
description:
X86: Fix the segment setting code in IRET, and make it restore the
flags.
diffstat:
1 file changed, 1 deletion(-)
changeset f33045b4dbee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f33045b4dbee
description:
X86: Make the I8259 PIC accept a specific EOI command.
diffstat:
2 files changed, 3 insertions(+), 2 deletions(-)
src/dev/x86/i8259.cc |4 ++--
src/dev/x86/i8259.hh |
changeset cec3cfa0b6b5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cec3cfa0b6b5
description:
X86: Make non-specific EOI commands work.
diffstat:
1 file changed, 2 insertions(+), 1 deletion(-)
src/dev/x86/i8259.cc |3 ++-
diffs (17 lines):
diff -r f33045b4dbee
changeset 0fee2dde61d7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0fee2dde61d7
description:
X86: Implement the EOI register in the local APIC.
diffstat:
1 file changed, 1 deletion(-)
src/arch/x86/interrupts.cc |1 -
diffs (26 lines):
diff -r bd70811ff2ef -r
changeset 28d6ff8b94e2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=28d6ff8b94e2
description:
X86: Make the local APIC timer event generate an interrupt.
diffstat:
2 files changed, 26 insertions(+)
src/arch/x86/interrupts.cc | 21 +
changeset 0d6addcde185 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0d6addcde185
description:
X86: Set the delayed commit flag in x86 microops appropriately.
diffstat:
1 file changed, 1 insertion(+)
src/arch/x86/isa/macroop.isa |1 +
diffs (49 lines):
diff -r
changeset e18928b6b108 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e18928b6b108
description:
X86: Make auto eoi mode work in the I8259 PIC.
diffstat:
1 file changed, 1 insertion(+)
src/dev/x86/i8259.hh |1 +
diffs (60 lines):
diff -r cec3cfa0b6b5 -r
changeset bd70811ff2ef in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bd70811ff2ef
description:
X86: Add some DPRINTFs to the local APIC.
diffstat:
1 file changed, 4 insertions(+), 2 deletions(-)
src/arch/x86/interrupts.cc |6 --
diffs (74 lines):
diff -r
changeset 4bf6f614871b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4bf6f614871b
description:
Get rid of some commented out code.
diffstat:
0 files changed
diffs (11 lines):
diff -r 0d6addcde185 -r 4bf6f614871b src/mem/tport.cc
--- a/src/mem/tport.cc Sun Oct 12
changeset de7a82f58985 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=de7a82f58985
description:
CPU: Explain why some code is commented out.
diffstat:
1 file changed, 2 insertions(+)
src/cpu/simple/atomic.cc |2 ++
diffs (14 lines):
diff -r 4bf6f614871b -r
See /z/m5/regression/regress-2008-10-13-03:00:01 for details.
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Hi Gabe,
I haven't looked at all the code surrounding this in detail, but I think
this is unnecessary... packets really are messages (though up to now they've
all been coherence messages), and the idea behind Port objects is that in
the common case a MemObject should have a dedicated Port
That sounds reasonable. I had originally envisioned this code having a use
outside of the interrupt messages, or at least in objects that wouldn't inherit
from IntDev to avoid multiple inheritance, etc, but if not then it doesn't need
to be in its own class.
Gabe
Quoting Steve Reinhardt [EMAIL
Thanks Steve!
By the way, I'll send out a revised version of the banked cache code later this
week.
Jiayuan
- Original Message -
From: Steve Reinhardt
To: M5 Developer List
Sent: 2008年10月13日 10:33 PM
Subject: Re: [m5-dev] submit patches: Mesh2D, directory coherence,and
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