changeset 25ae7c9393d9 in /z/repo/encumbered
details: http://repo.m5sim.org/encumbered?cmd=changeset;node=25ae7c9393d9
summary: these changes go with the changes I just pushed to m5 re: registering
a context
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
eio/eio.cc |2 +-
diffs (21
changeset 6ed48cba2217 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6ed48cba2217
description:
decouple eviction from insertion in the cache.
diffstat:
4 files changed, 6 insertions(+), 6 deletions(-)
src/mem/cache/tags/fa_lru.hh |2 +-
src/mem/cache/tags/iic.hh
changeset 76abee886def in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=76abee886def
description:
Add in Context IDs to the simulator. From now on, cpuId is almost
never used,
the primary identifier for a hardware context should be contextId().
The
changeset e8c1d4e669a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8c1d4e669a7
description:
get rid of all instances of readTid() and getThreadNum(). Unify and
eliminate
redundancies with threadId() as their replacement.
diffstat:
5 files changed, 5
changeset ee56bb539212 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ee56bb539212
description:
Change the findBlock(addr, lat) to accessBlock, which I think has
better connotations for what is really happening and how it should be used.
diffstat:
3 files changed, 11
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
passed.
*
changeset 993c7952b930 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=993c7952b930
description:
Make it so that all thread contexts are registered with the System,
even in
SE. Process still keeps track of the tc's it owns, but registration
occurs
with
Hey guys,
I'm trying to run a timing CMP with caches using EIO traces, but the EIO
can't seem to be run on multicore platforms, the 2nd cpu inevitably itb
pagefaults continually on a single PC (presumably the first) and then dies.
Is this a bug or a feature? Is there something I don't know
It's definitely a bug... it used to work. I wonder if it has
something to do with migrating towards a more realistic paging model
for SE mode (though that happened quite a while ago---August 2007
according to hg---and if that was totally broken I'm surprised no one
noticed it yet). I'd take a
changeset 199d31b47f7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=199d31b47f7b
description:
make BaseCPU the provider of _cpuId, and cpuId() instead of being
scattered
across the subclasses. generally make it so that member data is _cpuId
and
...and make a regression that catches the problem in the future.
Every time we find a bug that isn't caught by a regression test I
think we need to create a configuration that will catch it. In the
future we'll never miss it again, and the new regression might catch
other bugs that the
I figured out what I need to do to make the regression suite more
easily extensible. Yell at me if I don't actually do something to fix
it within a week.
Nate
On Tue, Nov 4, 2008 at 1:44 PM, Ali Saidi [EMAIL PROTECTED] wrote:
...and make a regression that catches the problem in the future.
This might be a reasonable fix for the immediate term, but I don't think
eio is limited to Alpha. A more appropriate place for this is probably
in the EIO process object constructor.
Gabe
[EMAIL PROTECTED] wrote:
changeset 2c7b9d01d542 in /z/repo/encumbered
details:
It happens in AlphaLiveProcess. I had the inclination that EIO is only
Alpha capable, I think I saw it on our wiki. Is that inherent or just the
way it is because we just don't have it for something else? I'm not sure
we'll develop eio for non-alpha anyway. But if people object, let me know,
I
EIO is Alpha only right now and will almost certainly remain so... not
because you couldn't port it to other ISAs, but if we decided we did
want to have an ISA-independent EIO-like capability we'd almost
certainly develop something else from scratch. The actual EIO code is
really there only for
I agree that it's not a very serious problem. I think I remember my
cubemate at HP trying to get SPARC EIO traces to work in M5 at one point
which is why I'm thinking they do exist, but if we want EIO to be Alpha
only I'm fine with that. Maybe we should put something like the
following in files
Looking into this more, there are two problems. First, it looks like
Alpha is passing back it's store conditional result in the extra data
part of the request. I think for regular swaps this is actually the data
to swap in, and for conditional swaps this is what to compare to, but
I'm not
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