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Sure, I will. I didn't make any changes really, but I think my code must be
different from yours by a little because for example I don't have function
tc-contextId()), instead I had to use tc-readCpuId()
I am not sure why our code base would be different and by how much, but that
could be why
I am doing it in m5.
Polina
On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote:
2009/3/5 Polina Dudnik pdud...@gmail.com:
I am not sure why our code base would be different and by how much, but
that
could be why yours is running fine and mine segfaults.
Hi Polina,
My output looks like this:
M5 compiled Mar 5 2009 13:51:37
M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff
qbase
M5 started Mar 5 2009 14:03:22
M5 executing on zeep
command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2
Global frequency set at 1 ticks
Yes, I am trying to figure it out right now by running it withing gdb. It is
pretty interesting that my output only differs from yours by one line which
is segfault.
It will be a little bit before I can install the most recent m5-dev because
the scons was upgraded to 0.98 and we are still on 0.97
If you want to get going quickly, you can download the scons-local
package and just stick it somewhere.
Nate
2009/3/5 Polina Dudnik pdud...@gmail.com:
Yes, I am trying to figure it out right now by running it withing gdb. It is
pretty interesting that my output only differs from yours by one
There's actually a bug in the CPU wakeup code which prevents any CPU
that isn't activated and then suspended, like SPARCs APs which are
suspended directly, from waking up on interrupts, etc. I have a
partial fix which I've been using to work around the problem, but we
need to come up with
On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu
wrote:
There's actually a bug in the CPU wakeup code which prevents any CPU
that isn't activated and then suspended, like SPARCs APs which are
suspended directly, from waking up on interrupts, etc. I have a
partial
changeset 886da6fa6d4a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=886da6fa6d4a
description:
SCons: Fix bug with .hg dir not existing.
diffstat:
1 file changed, 2 insertions(+), 3 deletions(-)
SConstruct |5 ++---
diffs (30 lines):
diff -r 4ed2100efa84 -r
There are multiple benchmarks that can be run in FS mode (like
ValStream). Where can I find a precise description of what those
benchmarks do exactly? The reason I ask is because I would like to
verify their behavior on SPARC_FS.
I don't know if much has been written down other than in papers
On Thu, Mar 5, 2009 at 4:50 PM, nathan binkert n...@binkert.org wrote:
There are multiple benchmarks that can be run in FS mode (like
ValStream). Where can I find a precise description of what those
benchmarks do exactly? The reason I ask is because I would like to
verify their behavior
Quoting Polina Dudnik pdud...@gmail.com:
On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu
wrote:
There's actually a bug in the CPU wakeup code which prevents any CPU
that isn't activated and then suspended, like SPARCs APs which are
suspended directly, from waking
Oh, I see. Do you think you can distribute the partial patch you have?
Thank you.
Polina
On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black gbl...@eecs.umich.edu
wrote:
Quoting Polina Dudnik pdud...@gmail.com:
On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black
The change is simple enough that I'll just describe it. This deals
solely with the simple CPU, so if your trying to use O3, for example,
it won't help you directly. The code here:
http://repo.m5sim.org/m5/file/886da6fa6d4a/src/cpu/simple/base.cc#l307
should return if the thread is
OK. Thanks. I will try that.
On Thu, Mar 5, 2009 at 5:10 PM, Gabriel Michael Black gbl...@eecs.umich.edu
wrote:
The change is simple enough that I'll just describe it. This deals
solely with the simple CPU, so if your trying to use O3, for example,
it won't help you directly. The code here:
I know why it wouldn't compile now. For some reason it just wasn't happy
with SUNW,Sun-Fire-880 but once I moved to SUNW,Sun-Fire-T200 it worked like
a charm!
On Tue, Mar 3, 2009 at 11:35 PM, Ali Saidi sa...@umich.edu wrote:
SUNW,Sun-Fire-T200
On Mar 3, 2009, at 9:48 PM, Polina wrote:
Hi
Just a note: you should NEVER have a 'using namespace' declaration at
the top level of a normal header file. This forces all the names in
that namespace into the global namespace of any source file including
that header file, which basically completely defeats the point of
namespaces.
It is OK
changeset 3ca926101a5c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3ca926101a5c
description:
Get rid of 'using namespace' declarations in headers.
diffstat:
8 files changed, 4 insertions(+), 19 deletions(-)
src/arch/alpha/linux/system.hh |5 +
Quoting Steve Reinhardt ste...@gmail.com:
On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote:
I think there are two possible solutions:
1. Add a retry response code for atomic requests (along the lines of
the error codes we alrady have in packet.hh) and then make sure that
On Thu, Mar 5, 2009 at 6:33 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Steve Reinhardt ste...@gmail.com:
On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote:
I think there are two possible solutions:
1. Add a retry response code for atomic requests
changeset 9c04119e93af in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9c04119e93af
description:
serialize: Allow floats and doubles to be serialized
diffstat:
1 file changed, 2 insertions(+)
src/sim/serialize.cc |2 ++
diffs (12 lines):
diff -r 3ca926101a5c -r
changeset 71e56052768f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=71e56052768f
description:
stats: miscellaneous cleanup
diffstat:
1 file changed, 7 insertions(+), 9 deletions(-)
src/base/statistics.hh | 16 +++-
diffs (82 lines):
diff -r
changeset 19131d568007 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19131d568007
description:
stats: get rid of meaningless uses of virtual
diffstat:
1 file changed, 79 insertions(+), 79 deletions(-)
src/base/statistics.hh | 158
changeset 2c9823c60c8c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2c9823c60c8c
description:
stats: better naming of template parameters for the wrapper stuff
Parent and Child are bad names. Derived and Base are better.
diffstat:
1 file changed, 25
changeset 7674070ccc92 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7674070ccc92
description:
stats: Add a wrapper class for the information side of things.
This provides an easy way to provide the callbacks into the data side
of things from the info
changeset 471090ec173e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=471090ec173e
description:
stats: stick the distribution's fancy parameter into the parameters
structure.
diffstat:
3 files changed, 22 insertions(+), 26 deletions(-)
src/base/statistics.hh | 23
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a4c935e9cf99
description:
stats: remove the template wart left over from the ancient binning stuff
diffstat:
1 file changed, 14 insertions(+), 28 deletions(-)
src/base/statistics.hh | 42
changeset 3cf8e71257e0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3cf8e71257e0
description:
stats: Fix all stats usages to deal with template fixes
diffstat:
50 files changed, 486 insertions(+), 486 deletions(-)
src/arch/alpha/kernel_stats.hh| 12
changeset 4f887be9e1b6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4f887be9e1b6
description:
stats: clean up how templates are used on the data side.
This basically works by taking advantage of the curiously recurring
template
pattern in an
changeset 00251eb95de7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00251eb95de7
description:
stats: create an enable phase, and a prepare phase.
Enable more or less takes the place of check, but also allows stats to
do some other configuration.
Just so everyone knows, this change fixes an old problem with the
template stuff left over from the binning days (for those of you that
remember). The thing that changes for people as a result is that the
name of the stat Classes has slightly changed.
We used to say things like
Stats::Scalar
Quoting Steve Reinhardt ste...@gmail.com:
On Thu, Mar 5, 2009 at 6:33 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Steve Reinhardt ste...@gmail.com:
On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote:
I think there are two possible solutions:
1. Add a
Here's another option: make the CPU model smart and when it sees a
lock access have it keep running until it sees an unlock access.
This might not be too bad if keep running could be implemented
simply by doing something like a recursive tail call to tick().
Steve
Here's another option: make the CPU model smart and when it sees a
lock access have it keep running until it sees an unlock access.
This might not be too bad if keep running could be implemented
simply by doing something like a recursive tail call to tick().
There's already a big loop in the
On Thu, Mar 5, 2009 at 7:40 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
I like that option the best so far. I'll assume that's what we're
doing unless I suddenly think of a compelling reason not to or if
someone doesn't like it.
Great... it should be even easier than I thought if
How different are ITBs and DTBs anyway? It seems like for a UTB you'd
want a single object that handles both ifetch and data translations
using a common translate() method, not something that inherits from
two different classes. E.g., why not just derive it from TLB?
The two translation
On Thu, Mar 5, 2009 at 9:09 PM, nathan binkert n...@binkert.org wrote:
How different are ITBs and DTBs anyway? It seems like for a UTB you'd
want a single object that handles both ifetch and data translations
using a common translate() method, not something that inherits from
two different
I believe the reason the UTB thing was done in that way was to try to match
the current M5 infrastructure which require ITB and DTB pointers in every
CPU model and have a few functions that hardcode (itb-___ or dtb-___).
If you dont derive UTB from both ITB and DTB you'll have a problem there
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