Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData + TLB miss
Off hand I would say yes, queuing up a second request behind one that caused a table walk makes sense. Since there should only be one other request, just having a variable for the on deck request should be sufficient instead of a full blown queue. Please let me know if you think otherwise. I'll think about it some more and let you know if I change my mind, but I think that makes sense. Gabe Quoting Joel Hestness : Hi, I am currently running a benchmark in X86_FS timing mode (single or multicore) that crashes due to the page table walker. On a data write (or read) instruction that causes TimingSimpleCPU::write to split the TLB access into two accesses (cpu/simple/timing.cc:~560), if the first TLB access misses, it causes the page table walker to start a walk and its state = Waiting. Since the second access happens immediately in TimingSimpleCPU::write, if the second request also misses, it causes another walk that fails the (state == Ready) assertion in X86ISA::Walker::start (arch/x86/pagetable_walker.cc:~316). Seems this is a corner case of a corner case, namely, an unaligned (split) data access, whose split TLB accesses both miss. It doesn't look like there is any code to handle the situation yet, and I'm hoping to get some guidance on how to address it. It seems to me that since this only happens on a TLB miss, that the TLB or walker should be able to handle the multiple requests. I see that in the ARM code, the page table walker has a queue of walks that are currently in flight (I'm having trouble convincing myself that the queues can't conflict when multiple walks are in flight :\). Would it make sense to have similar state queuing in the x86 page table walker? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] TimingSimpleCPU, x86: sendSplitData + TLB miss
Hi, I am currently running a benchmark in X86_FS timing mode (single or multicore) that crashes due to the page table walker. On a data write (or read) instruction that causes TimingSimpleCPU::write to split the TLB access into two accesses (cpu/simple/timing.cc:~560), if the first TLB access misses, it causes the page table walker to start a walk and its state = Waiting. Since the second access happens immediately in TimingSimpleCPU::write, if the second request also misses, it causes another walk that fails the (state == Ready) assertion in X86ISA::Walker::start (arch/x86/pagetable_walker.cc:~316). Seems this is a corner case of a corner case, namely, an unaligned (split) data access, whose split TLB accesses both miss. It doesn't look like there is any code to handle the situation yet, and I'm hoping to get some guidance on how to address it. It seems to me that since this only happens on a TLB miss, that the TLB or walker should be able to handle the multiple requests. I see that in the ARM code, the page table walker has a queue of walks that are currently in flight (I'm having trouble convincing myself that the queues can't conflict when multiple walks are in flight :\). Would it make sense to have similar state queuing in the x86 page table walker? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: STATS: Fix off-by-one error in distributions.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/203/ --- Review request for Default. Summary --- STATS: Fix off-by-one error in distributions. bkt size isn't evenly divisible by max-min and it would round down, it's possible to sample a distribution and have no place to put the sample. When this case occured the simulator would assert. Diffs - src/base/statistics.hh 3c48b2b3cb83 Diff: http://reviews.m5sim.org/r/203/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Next Tasks for GEM5
Hi All, Yesterday a few of us from AMD and Wisconsin met and discussed the next tasks for GEM5. Specifically there are a couple (possibly more?) new graduate students at Wisconsin that are starting to ramp up in the simulator. While we spent some time discussing short-term projects for the new graduate students, the majority of the time was focused on a remaining steps necessary before Ruby can supply data to M5 cpus while using warmed up cache traces. Below is a summary of our meeting as well as a discussion on the possible directions we can take. I'm send this summary out so that other can comment and provide feedback. Please let me know if you have any questions, Brad Short-term projects for the new Wisconsin graduate students - Incorporate work completed/transaction completed metrics to Simulate.py - Include randomization support into the memory system to simulate multiple execution paths Tasks required before Ruby can supply data to M5 cpus while using a warmed up cache traces. - Add support for cache flushes within the protocols o This mechanism is required by certain x86 instructions and memory types o Furthermore it could be leveraged to create checkpoints that include both valid main memory data as well as a cache warmup trace with valid data. (More on this topic below) - Provide support for allowing certain simobjects to be scheduled on the event queue without advancing sim_ticks o In order to run a cache warmup trace through Ruby, Ruby requests need to be executed and Ruby simobjects need to be scheduled. However, at the end of warmup, the simticks and the rest of the simulator state need to be consistent with the loaded checkpoint. § Currently, we (at AMD) have an internal patch that achieves this functionality by leveraging the fact that Ruby objects still use the Ruby eventqueue API. During this warmup phase, the Ruby eventqueue detaches from the M5 event queue and instead uses the old ruby event queue implementation to schedule events. Once the warmup is complete, the Ruby eventqueue reattaches to the M5 event queue. This obviously is not the real way we want to do this because eventually we want all Ruby events to directly use the M5 event queue API. That is why I don't have plans to check in this current patch to the public tree. o One possible solution would be to identify which events can be scheduled during cache warmup and assume all other events can only be scheduled during actual execution. § I'm interested to know how complicated others believe a solution like that would be? - Once the two above tasks are complete, we should be able to create cache warmup traces with data and also provide valid data in main memory. o The motivation for providing valid data in both the cache trace and main memory is that we maintain the flexibility of allowing each protocol to create their own policies for handling dirty data. o The specific mechanism would be to record the cache trace using Ruby's current CacheRecorder (I've already revitalized this code in GEM5) and then use the cache flush mechanism to flush dirty data to main memory before checkpointing memory. - Add functional access support to Ruby. o One possible way to add functional access support to Ruby is to quiesce or drain outstanding Ruby requests when a dynamic functional access is initiated and actually perform the access after Ruby has been drained of any outstanding requests. § Therefore, if all cache blocks are in a base state, then Ruby can use the protocol independent AccessPremissions on the cache and data blocks to determine which blocks should be read and written. This would only require additional set state operations in the Directory sm files to set the AccessPremissions for a block. The cache sm files already do this so the impact to the protocols would be minimal. § However, the obvious disadvantage to this approach is that every functional access will perturb the timing of the system. o Another possible approach is to add atomic access support to Ruby and utilize this for functional accesses. § Basically instead of using events resulting from the receiving of timed messages to transition between base states, use function calls. § I'm not sure how to make this work, and I fear that it will restrict how protocols are defined. Furthermore, it seems it would be extremely complicated to get these atomic accesses to work while timing accesses are active in the system and cache blocks are already in some sort of transient state. Overall, I suspect this is not easily feasible, but I could be wrong. o A third option is to restrict functional writes to only initialization and allow dynamic functional reads to be only a best effort and not guaranteed to be correct. § I believe Steve has already discussed such a possibility with Nate and Ali. § Functional writes
Re: [m5-dev] Cron /z/m5/regression/do-regression quick
The "Statistics Differences" line doesn't mean anything, that gets printed even if there aren't any changes. It's just a fluke of interleaved outputs when those get printed out by grep. They all passed before I committed, so it's probably some minor thing; I see that it's the Ruby test for the default protocol so maybe I have an environment var set that makes it behave differently on my machine. If anyone has any reason to think it's more significant let me know, as I may not have time to get to it today (or even in the next few days), because I'm traveling. Steve On Wed, Aug 18, 2010 at 9:28 AM, Gabe Black wrote: > I see one failure but two occurrences of "Statistics differences". You > were the only one to check something in yesterday, Steve. > > Gabe > > Cron Daemon wrote: >> * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby >> FAILED! >> * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic >> passed. >> = Statistics differences =* >> build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing >> passed. >> * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing >> passed. >> * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. >> * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic >> passed. >> * >> build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby >> passed. >> * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing >> passed. >> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. >> * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp >> passed. >> * >> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer >> passed. >> * >> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer >> passed. >> * >> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer >> passed. >> * >> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer >> passed. >> * >> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory >> passed. >> * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. >> * >> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token >> passed. >> * >> build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token >> passed. >> * >> build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic >> passed. >> * >> build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual >> passed. >> * >> build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing >> passed. >> * >> build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual >> passed. >> * >> build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic >> passed. >> * build/MIPS_SE/tests/fast/quick/00.hello
Re: [m5-dev] Cron /z/m5/regression/do-regression quick
I see one failure but two occurrences of "Statistics differences". You were the only one to check something in yesterday, Steve. Gabe Cron Daemon wrote: > * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby > FAILED! > * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic > passed. > = Statistics differences =* > build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing > passed. > * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing > passed. > * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. > * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby > passed. > * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing > passed. > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. > * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp > passed. > * > build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer > passed. > * > build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer > passed. > * > build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer > passed. > * > build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer > passed. > * > build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory > passed. > * > build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory > passed. > * > build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory > passed. > * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. > * > build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory > passed. > * > build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory > passed. > * > build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory > passed. > * > build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory > passed. > * > build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory > passed. > * > build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token > passed. > * > build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token > passed. > * > build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token > passed. > * > build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token > passed. > * > build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic > passed. > * > build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual > passed. > * > build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing > passed. > * > build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual > passed. > * > build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic > passed. > * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby > passed. > * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. > * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. > * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed. > * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing > passed. > * build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic > passed. > * build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed. > * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing > passed. > * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic > passed. > * build/SPARC_SE/tests/
[m5-dev] Cron /z/m5/regression/do-regression quick
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. = Statistics differences =* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/
