[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp FAILED! * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic FAILED! * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
Re: [m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
Not me I hope. File system issues again? Cron Daemon wrote: * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp FAILED! * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic FAILED! ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: X86: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/307/ --- Review request for Default. Summary --- X86: Take advantage of new PCState syntax. Diffs - src/arch/x86/isa/decoder/two_byte_opcodes.isa f440cdaf1c2d src/arch/x86/isa/microops/regop.isa f440cdaf1c2d src/arch/x86/isa/microops/seqop.isa f440cdaf1c2d src/arch/x86/isa/operands.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/307/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: SPARC: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/308/ --- Review request for Default. Summary --- SPARC: Take advantage of new PCState syntax. Diffs - src/arch/sparc/isa/decoder.isa f440cdaf1c2d src/arch/sparc/isa/formats/branch.isa f440cdaf1c2d src/arch/sparc/isa/operands.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/308/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: POWER: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/309/ --- Review request for Default. Summary --- POWER: Take advantage of new PCState syntax. Diffs - src/arch/power/isa/decoder.isa f440cdaf1c2d src/arch/power/isa/formats/branch.isa f440cdaf1c2d src/arch/power/isa/operands.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/309/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: MIPS: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/310/ --- Review request for Default. Summary --- MIPS: Take advantage of new PCState syntax. Diffs - src/arch/mips/isa/decoder.isa f440cdaf1c2d src/arch/mips/isa/formats/branch.isa f440cdaf1c2d src/arch/mips/isa/operands.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/310/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: Alpha: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/311/ --- Review request for Default. Summary --- Alpha: Take advantage of new PCState syntax. Diffs - src/arch/alpha/isa/branch.isa f440cdaf1c2d src/arch/alpha/isa/decoder.isa f440cdaf1c2d src/arch/alpha/isa/main.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/311/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: ARM: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/ --- Review request for Default. Summary --- ARM: Take advantage of new PCState syntax. Diffs - src/arch/arm/isa/insts/branch.isa f440cdaf1c2d src/arch/arm/isa/insts/data.isa f440cdaf1c2d src/arch/arm/isa/insts/ldr.isa f440cdaf1c2d src/arch/arm/isa/insts/macromem.isa f440cdaf1c2d src/arch/arm/isa/insts/misc.isa f440cdaf1c2d src/arch/arm/isa/operands.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/312/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: ISA: Get the parser to support pc state components more elegantly.
This change implements the ISA parser part of new syntax to read and write components of the PCState more like the old syntax. Things center around the PCState operand type, it's default ctype, and its register index. When manipulating the PC state object as a whole, the ctype is set to None and automatically becomes TheISA::PCState, and the index is also set to None. When dealing with components, ctype describes the type for the extracted component and the register index specifier is used as the name of the accessor function. The six subsequent patches update each of the ISAs to use the new syntax. These could use more testing, as usual especially ARM, but I wanted to get them out there before I started traveling. Gabe Gabe Black wrote: This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/306/ Review request for Default. By Gabe Black. Description ISA: Get the parser to support pc state components more elegantly. Diffs * src/arch/isa_parser.py (f440cdaf1c2d) View Diff http://reviews.m5sim.org/r/306/diff/ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
Pretty sure it is... I'll try to move a copy to zizzer soon. Ali On Nov 15, 2010, at 2:15 AM, Gabe Black wrote: Not me I hope. File system issues again? Cron Daemon wrote: * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp FAILED! * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic FAILED! ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] isa_parser debug mode
Sounds reasonable to me too. Should we have a single flag that enables tracebacks in both the parser and in the rest of python? IIRC, we print the python backtrace by default when we hit a python exception, and it seems to me that most of the time the backtrace obscures a useful error message rather than providing any help (though of course sometimes it's the other way around). Steve On Sun, Nov 14, 2010 at 9:37 PM, nathan binkert n...@binkert.org wrote: Seems fine to me. --debug already exists with scons, so that's perhaps not the best option. I think we want to try to kee our options separate from SCons. Nate On Sun, Nov 14, 2010 at 7:41 PM, Gabe Black gbl...@eecs.umich.edu wrote: Hi everybody. If you don't actively work on ISA descriptions or the parser, feel free to ignore this email. I've been working on the parser to better integrate the recent PC changes, and it's been useful to turn on the backtrace feature of the parser by setting debug=True at the top. This is a lot better than having it buried in the script (thanks, Ali) but it's still fairly easy to forget to turn it back off when generating patches, etc. Would anyone object to plumbing a scons variable through scons and into the parser to affect that behavior? I'm not sure whether a command line variable or -- style option would be best for scons, but I'm leaning heavily towards something like --debug for the parser itself. This isn't high priority and I may never bother actually implementing it, but I wanted to see if anyone violently apposed for some reason, maybe the added complexity and leaking of parser control knobs into the wider world of scons. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: ISA: Get the parser to support pc state components more elegantly.
Nice! I just skimmed the code quickly, but it looks good to me. Steve On Mon, Nov 15, 2010 at 4:35 AM, Gabe Black gbl...@eecs.umich.edu wrote: This change implements the ISA parser part of new syntax to read and write components of the PCState more like the old syntax. Things center around the PCState operand type, it's default ctype, and its register index. When manipulating the PC state object as a whole, the ctype is set to None and automatically becomes TheISA::PCState, and the index is also set to None. When dealing with components, ctype describes the type for the extracted component and the register index specifier is used as the name of the accessor function. The six subsequent patches update each of the ISAs to use the new syntax. These could use more testing, as usual especially ARM, but I wanted to get them out there before I started traveling. Gabe Gabe Black wrote: This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/306/ Review request for Default. By Gabe Black. Description ISA: Get the parser to support pc state components more elegantly. Diffs * src/arch/isa_parser.py (f440cdaf1c2d) View Diff http://reviews.m5sim.org/r/306/diff/ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Make O3 support variably lengthed instructions.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/281/#review481 --- Ship it! - Ali On 2010-11-11 04:44:28, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/281/ --- (Updated 2010-11-11 04:44:28) Review request for Default. Summary --- O3: Make O3 support variably lengthed instructions. Diffs - src/arch/alpha/predecoder.hh 340b6f01d69b src/arch/mips/predecoder.hh 340b6f01d69b src/arch/power/predecoder.hh 340b6f01d69b src/arch/sparc/predecoder.hh 340b6f01d69b src/cpu/base.hh 340b6f01d69b src/cpu/o3/fetch.hh 340b6f01d69b src/cpu/o3/fetch_impl.hh 340b6f01d69b src/cpu/simple/base.hh 340b6f01d69b Diff: http://reviews.m5sim.org/r/281/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: ARM: Do something predictable for an UNPREDICTA...
changeset 9e11081542e4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9e11081542e4
description:
ARM: Do something predictable for an UNPREDICTABLE branch.
diffstat:
src/arch/arm/types.hh | 4
1 files changed, 4 insertions(+), 0 deletions(-)
diffs (14 lines):
diff -r f440cdaf1c2d -r 9e11081542e4 src/arch/arm/types.hh
--- a/src/arch/arm/types.hh Thu Nov 11 11:58:09 2010 -0800
+++ b/src/arch/arm/types.hh Mon Nov 15 14:04:03 2010 -0600
@@ -333,6 +333,10 @@
nextThumb(false);
} else {
warn(Bad interworking branch address %#x.\n, newPC);
+// This state is UNPREDICTABLE in the ARM architecture
+// The easy thing to do is just mask off the bit and
+// stay in the current mode, so we'll do that.
+newPC = ~mask(2);
}
}
npc(newPC);
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[m5-dev] changeset in m5: ARM: Fix SRS instruction to micro-code memory o...
changeset 79adfecb2b8a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=79adfecb2b8a description: ARM: Fix SRS instruction to micro-code memory operation and register update. Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect. diffstat: src/arch/arm/isa/insts/str.isa | 11 --- 1 files changed, 8 insertions(+), 3 deletions(-) diffs (32 lines): diff -r 434b5dfb87d9 -r 79adfecb2b8a src/arch/arm/isa/insts/str.isa --- a/src/arch/arm/isa/insts/str.isaMon Nov 15 14:04:03 2010 -0600 +++ b/src/arch/arm/isa/insts/str.isaMon Nov 15 14:04:03 2010 -0600 @@ -112,8 +112,6 @@ Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) | ((uint64_t)cSwap(Spsr.uw, cpsr.e) 32); ''' -if self.writeback: -accCode += SpMode = SpMode + %s;\n % wbDiff global header_output, decoder_output, exec_output @@ -122,11 +120,18 @@ postacc_code: } codeBlobs[predicate_test] = pickPredicate(codeBlobs) +wbDecl = None +if self.writeback: +wbDecl = '''MicroAddiUop(machInst, + intRegInMode((OperatingMode)regMode, INTREG_SP), + intRegInMode((OperatingMode)regMode, INTREG_SP), + %d);''' % wbDiff + (newHeader, newDecoder, newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, [ArmISA::TLB::AlignWord, ArmISA::TLB::MustBeOne], [], - base = 'SrsOp') + 'SrsOp', wbDecl) header_output += newHeader decoder_output += newDecoder ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: CPU: Fix bug when a split transaction is issued...
changeset 434b5dfb87d9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=434b5dfb87d9
description:
CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a
CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
diffstat:
src/cpu/simple/timing.cc | 11 ++-
src/cpu/simple/timing.hh | 4 +++-
2 files changed, 13 insertions(+), 2 deletions(-)
diffs (48 lines):
diff -r 9e11081542e4 -r 434b5dfb87d9 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/cpu/simple/timing.cc Mon Nov 15 14:04:03 2010 -0600
@@ -999,7 +999,16 @@
if (next_tick == curTick) {
cpu-completeDataAccess(pkt);
} else {
-tickEvent.schedule(pkt, next_tick);
+if (!tickEvent.scheduled()) {
+tickEvent.schedule(pkt, next_tick);
+} else {
+// In the case of a split transaction and a cache that is
+// faster than a CPU we could get two responses before
+// next_tick expires
+if (!retryEvent.scheduled())
+schedule(retryEvent, next_tick);
+return false;
+}
}
return true;
diff -r 9e11081542e4 -r 434b5dfb87d9 src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/cpu/simple/timing.hh Mon Nov 15 14:04:03 2010 -0600
@@ -140,7 +140,7 @@
public:
CpuPort(const std::string _name, TimingSimpleCPU *_cpu, Tick _lat)
-: Port(_name, _cpu), cpu(_cpu), lat(_lat)
+: Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
{ }
bool snoopRangeSent;
@@ -161,12 +161,14 @@
{
PacketPtr pkt;
TimingSimpleCPU *cpu;
+CpuPort *port;
TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
const char *description() const { return Timing CPU tick; }
void schedule(PacketPtr _pkt, Tick t);
};
+EventWrapperPort, Port::sendRetry retryEvent;
};
class IcachePort : public CpuPort
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[m5-dev] changeset in m5: ARM: Use the correct delete operator for RFE
changeset 2b65eb281f5f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2b65eb281f5f
description:
ARM: Use the correct delete operator for RFE
diffstat:
src/arch/arm/insts/mem.hh | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r 79adfecb2b8a -r 2b65eb281f5f src/arch/arm/insts/mem.hh
--- a/src/arch/arm/insts/mem.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/insts/mem.hh Mon Nov 15 14:04:03 2010 -0600
@@ -110,7 +110,7 @@
virtual
~RfeOp()
{
-delete uops;
+delete [] uops;
}
StaticInstPtr
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[m5-dev] changeset in m5: ARM: Add support for switching CPUs
changeset 7bf78d12b359 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7bf78d12b359
description:
ARM: Add support for switching CPUs
diffstat:
src/arch/arm/table_walker.cc | 16 ++--
src/arch/arm/table_walker.hh | 1 +
src/arch/arm/utility.cc | 17 +
src/arch/arm/utility.hh | 6 +-
4 files changed, 33 insertions(+), 7 deletions(-)
diffs (94 lines):
diff -r 2b65eb281f5f -r 7bf78d12b359 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/table_walker.cc Mon Nov 15 14:04:03 2010 -0600
@@ -43,6 +43,7 @@
#include dev/io_device.hh
#include cpu/base.hh
#include cpu/thread_context.hh
+#include sim/system.hh
using namespace ArmISA;
@@ -59,9 +60,10 @@
}
-unsigned int TableWalker::drain(Event *de)
+unsigned int
+TableWalker::drain(Event *de)
{
-if (stateQueueL1.size() != 0 || stateQueueL2.size() != 0)
+if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
{
changeState(Draining);
DPRINTF(Checkpoint, TableWalker busy, wait to drain\n);
@@ -75,6 +77,16 @@
}
}
+void
+TableWalker::resume()
+{
+MemObject::resume();
+if ((params()-sys-getMemoryMode() == Enums::timing) currState) {
+delete currState;
+currState = NULL;
+}
+}
+
Port*
TableWalker::getPort(const std::string if_name, int idx)
{
diff -r 2b65eb281f5f -r 7bf78d12b359 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/table_walker.hh Mon Nov 15 14:04:03 2010 -0600
@@ -351,6 +351,7 @@
}
virtual unsigned int drain(Event *de);
+virtual void resume();
virtual Port *getPort(const std::string if_name, int idx = -1);
Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
diff -r 2b65eb281f5f -r 7bf78d12b359 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/utility.cc Mon Nov 15 14:04:03 2010 -0600
@@ -133,5 +133,22 @@
tc-pcState(newPC);
}
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+int i;
+for(i = 0; i TheISA::NumIntRegs; i++)
+dest-setIntReg(i, src-readIntReg(i));
+for(i = 0; i TheISA::NumFloatRegs; i++)
+dest-setFloatReg(i, src-readFloatReg(i));
+for(i = 0; i TheISA::NumMiscRegs; i++)
+dest-setMiscRegNoEffect(i, src-readMiscRegNoEffect(i));
+// setMiscReg with effect will set the misc register mapping correctly.
+// e.g. updateRegMap(val)
+dest-setMiscReg(MISCREG_CPSR, src-readMiscRegNoEffect(MISCREG_CPSR));
+
+// Lastly copy PC/NPC
+dest-pcState(src-pcState());
}
+}
diff -r 2b65eb281f5f -r 7bf78d12b359 src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/utility.hh Mon Nov 15 14:04:03 2010 -0600
@@ -102,11 +102,7 @@
tc-activate(0);
}
-static inline void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-panic(Copy Regs Not Implemented Yet\n);
-}
+void copyRegs(ThreadContext *src, ThreadContext *dest);
static inline void
copyMiscRegs(ThreadContext *src, ThreadContext *dest)
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller
changeset 0731d632db76 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0731d632db76
description:
ARM: Add support for a dumb IDE controller
diffstat:
configs/common/FSConfig.py | 10 ++
src/dev/Ide.py | 2 ++
src/dev/arm/realview.cc| 6 ++
src/dev/ide_ctrl.cc| 16 +++-
src/dev/ide_ctrl.hh| 2 ++
src/dev/pcidev.cc | 3 ++-
6 files changed, 33 insertions(+), 6 deletions(-)
diffs (119 lines):
diff -r 859e8bc1cdc2 -r 0731d632db76 configs/common/FSConfig.py
--- a/configs/common/FSConfig.pyMon Nov 15 14:04:03 2010 -0600
+++ b/configs/common/FSConfig.pyMon Nov 15 14:04:03 2010 -0600
@@ -209,6 +209,16 @@
self.mem_mode = mem_mode
+#self.cf0 = CowIdeDisk(driveID='master')
+#self.cf0.childImage(mdesc.disk())
+#self.cf_ctrl = IdeController(disks=[self.cf0],
+# pci_func = 0, pci_dev = 0, pci_bus = 0,
+# io_shift = 1, ctrl_offset = 2, Command = 0x1,
+# BAR0 = 0x1800, BAR0Size = '16B',
+# BAR1 = 0x18000100, BAR1Size = '1B',
+# BAR0LegacyIO = True, BAR1LegacyIO = True,)
+#self.cf_ctrl.pio = self.iobus.port
+
if machine_type == RealView_PBX:
self.realview = RealViewPBX()
elif machine_type == RealView_EB:
diff -r 859e8bc1cdc2 -r 0731d632db76 src/dev/Ide.py
--- a/src/dev/Ide.pyMon Nov 15 14:04:03 2010 -0600
+++ b/src/dev/Ide.pyMon Nov 15 14:04:03 2010 -0600
@@ -64,3 +64,5 @@
BAR3Size = '4B'
BAR4Size = '16B'
+io_shift = Param.UInt32(0x0, IO port shift);
+ctrl_offset = Param.UInt32(0x0, IDE disk control offset)
diff -r 859e8bc1cdc2 -r 0731d632db76 src/dev/arm/realview.cc
--- a/src/dev/arm/realview.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/dev/arm/realview.cc Mon Nov 15 14:04:03 2010 -0600
@@ -108,15 +108,13 @@
Addr
RealView::calcPciConfigAddr(int bus, int dev, int func)
{
-panic(Need implementation\n);
-M5_DUMMY_RETURN
+return ULL(-1);
}
Addr
RealView::calcPciIOAddr(Addr addr)
{
-panic(Need implementation\n);
-M5_DUMMY_RETURN
+return addr;
}
Addr
diff -r 859e8bc1cdc2 -r 0731d632db76 src/dev/ide_ctrl.cc
--- a/src/dev/ide_ctrl.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/dev/ide_ctrl.cc Mon Nov 15 14:04:03 2010 -0600
@@ -84,7 +84,8 @@
primaryTiming(htole(timeRegWithDecodeEn)),
secondaryTiming(htole(timeRegWithDecodeEn)),
deviceTiming(0), udmaControl(0), udmaTiming(0), ideConfig(0),
-ioEnabled(false), bmEnabled(false)
+ioEnabled(false), bmEnabled(false),
+ioShift(p-io_shift), ctrlOffset(p-ctrl_offset)
{
if (params()-disks.size() 3)
panic(IDE controllers support a maximum of 4 devices attached!\n);
@@ -106,6 +107,15 @@
primary.select(false);
secondary.select(false);
+if ((BARAddrs[0] ~BAR_IO_MASK) != 0){
+primary.cmdAddr = BARAddrs[0]; primary.cmdSize = BARSize[0];
+primary.ctrlAddr = BARAddrs[1]; primary.ctrlSize = BARAddrs[1];
+}
+if ((BARAddrs[2] ~BAR_IO_MASK) != 0){
+secondary.cmdAddr = BARAddrs[2]; secondary.cmdSize = BARSize[2];
+secondary.ctrlAddr = BARAddrs[3]; secondary.ctrlSize = BARAddrs[3];
+}
+
ioEnabled = (config.command htole(PCI_CMD_IOSE));
bmEnabled = (config.command htole(PCI_CMD_BME));
}
@@ -441,10 +451,14 @@
if (addr = primary.cmdAddr
addr (primary.cmdAddr + primary.cmdSize)) {
addr -= primary.cmdAddr;
+// linux may have shifted the address by ioShift,
+// here we shift it back, similarly for ctrlOffset.
+addr = ioShift;
primary.accessCommand(addr, size, dataPtr, read);
} else if (addr = primary.ctrlAddr
addr (primary.ctrlAddr + primary.ctrlSize)) {
addr -= primary.ctrlAddr;
+addr += ctrlOffset;
primary.accessControl(addr, size, dataPtr, read);
} else if (addr = secondary.cmdAddr
addr (secondary.cmdAddr + secondary.cmdSize)) {
diff -r 859e8bc1cdc2 -r 0731d632db76 src/dev/ide_ctrl.hh
--- a/src/dev/ide_ctrl.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/dev/ide_ctrl.hh Mon Nov 15 14:04:03 2010 -0600
@@ -133,6 +133,8 @@
bool ioEnabled;
bool bmEnabled;
+uint32_t ioShift, ctrlOffset;
+
void dispatchAccess(PacketPtr pkt, bool read);
public:
diff -r 859e8bc1cdc2 -r 0731d632db76 src/dev/pcidev.cc
--- a/src/dev/pcidev.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/dev/pcidev.cc Mon Nov 15 14:04:03 2010 -0600
@@ -76,7 +76,8 @@
bool snoop)
{
snoop = false;;
-resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
+if (configAddr != ULL(-1))
+resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
}
___
m5-dev
[m5-dev] changeset in m5: ARM: Make utility.hh meet style guidelines
changeset b12a5700f1fa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b12a5700f1fa
description:
ARM: Make utility.hh meet style guidelines
diffstat:
src/arch/arm/utility.hh | 168
1 files changed, 84 insertions(+), 84 deletions(-)
diffs (192 lines):
diff -r 0731d632db76 -r b12a5700f1fa src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/utility.hh Mon Nov 15 14:04:03 2010 -0600
@@ -56,104 +56,104 @@
namespace ArmISA {
-inline PCState
-buildRetPC(const PCState curPC, const PCState callPC)
+inline PCState
+buildRetPC(const PCState curPC, const PCState callPC)
+{
+PCState retPC = callPC;
+retPC.uEnd();
+return retPC;
+}
+
+inline bool
+testPredicate(CPSR cpsr, ConditionCode code)
+{
+switch (code)
{
-PCState retPC = callPC;
-retPC.uEnd();
-return retPC;
+case COND_EQ: return cpsr.z;
+case COND_NE: return !cpsr.z;
+case COND_CS: return cpsr.c;
+case COND_CC: return !cpsr.c;
+case COND_MI: return cpsr.n;
+case COND_PL: return !cpsr.n;
+case COND_VS: return cpsr.v;
+case COND_VC: return !cpsr.v;
+case COND_HI: return (cpsr.c !cpsr.z);
+case COND_LS: return !(cpsr.c !cpsr.z);
+case COND_GE: return !(cpsr.n ^ cpsr.v);
+case COND_LT: return (cpsr.n ^ cpsr.v);
+case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
+case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
+case COND_AL: return true;
+case COND_UC: return true;
+default:
+panic(Unhandled predicate condition: %d\n, code);
}
+}
-inline bool
-testPredicate(CPSR cpsr, ConditionCode code)
-{
-switch (code)
-{
-case COND_EQ: return cpsr.z;
-case COND_NE: return !cpsr.z;
-case COND_CS: return cpsr.c;
-case COND_CC: return !cpsr.c;
-case COND_MI: return cpsr.n;
-case COND_PL: return !cpsr.n;
-case COND_VS: return cpsr.v;
-case COND_VC: return !cpsr.v;
-case COND_HI: return (cpsr.c !cpsr.z);
-case COND_LS: return !(cpsr.c !cpsr.z);
-case COND_GE: return !(cpsr.n ^ cpsr.v);
-case COND_LT: return (cpsr.n ^ cpsr.v);
-case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
-case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
-case COND_AL: return true;
-case COND_UC: return true;
-default:
-panic(Unhandled predicate condition: %d\n, code);
-}
-}
+/**
+ * Function to insure ISA semantics about 0 registers.
+ * @param tc The thread context.
+ */
+template class TC
+void zeroRegisters(TC *tc);
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template class TC
-void zeroRegisters(TC *tc);
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{
+tc-activate(0);
+}
-inline void startupCPU(ThreadContext *tc, int cpuId)
-{
-tc-activate(0);
-}
+void copyRegs(ThreadContext *src, ThreadContext *dest);
-void copyRegs(ThreadContext *src, ThreadContext *dest);
+static inline void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+panic(Copy Misc. Regs Not Implemented Yet\n);
+}
-static inline void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-panic(Copy Misc. Regs Not Implemented Yet\n);
-}
+void initCPU(ThreadContext *tc, int cpuId);
-void initCPU(ThreadContext *tc, int cpuId);
-
-static inline bool
-inUserMode(CPSR cpsr)
-{
-return cpsr.mode == MODE_USER;
-}
+static inline bool
+inUserMode(CPSR cpsr)
+{
+return cpsr.mode == MODE_USER;
+}
-static inline bool
-inUserMode(ThreadContext *tc)
-{
-return inUserMode(tc-readMiscRegNoEffect(MISCREG_CPSR));
-}
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+return inUserMode(tc-readMiscRegNoEffect(MISCREG_CPSR));
+}
-static inline bool
-inPrivilegedMode(CPSR cpsr)
-{
-return !inUserMode(cpsr);
-}
+static inline bool
+inPrivilegedMode(CPSR cpsr)
+{
+return !inUserMode(cpsr);
+}
-static inline bool
-inPrivilegedMode(ThreadContext *tc)
-{
-return !inUserMode(tc);
-}
+static inline bool
+inPrivilegedMode(ThreadContext *tc)
+{
+return !inUserMode(tc);
+}
-static inline bool
-vfpEnabled(CPACR cpacr, CPSR cpsr)
-{
-return cpacr.cp10 == 0x3 ||
-(cpacr.cp10 == 0x1 inPrivilegedMode(cpsr));
-}
+static inline bool
+vfpEnabled(CPACR cpacr, CPSR cpsr)
+{
+return cpacr.cp10 == 0x3 ||
+(cpacr.cp10 == 0x1 inPrivilegedMode(cpsr));
+}
-static inline bool
-vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC
[m5-dev] changeset in m5: ARM: Add support for GDB on ARM
changeset 08e1e28a062a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=08e1e28a062a
description:
ARM: Add support for GDB on ARM
diffstat:
src/arch/arm/SConscript|1 +
src/arch/arm/remote_gdb.cc | 346 +
src/arch/arm/remote_gdb.hh | 45 +++--
src/arch/arm/utility.cc| 13 +
src/arch/arm/utility.hh|3 +
5 files changed, 389 insertions(+), 19 deletions(-)
diffs (truncated from 457 to 300 lines):
diff -r b12a5700f1fa -r 08e1e28a062a src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/SConscript Mon Nov 15 14:04:03 2010 -0600
@@ -60,6 +60,7 @@
Source('nativetrace.cc')
Source('tlb.cc')
Source('utility.cc')
+Source('remote_gdb.cc')
SimObject('ArmNativeTrace.py')
SimObject('ArmTLB.py')
diff -r b12a5700f1fa -r 08e1e28a062a src/arch/arm/remote_gdb.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/arch/arm/remote_gdb.ccMon Nov 15 14:04:03 2010 -0600
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * William Wang
+ */
+
+/*
+ * Copyright (c) 1990, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Lawrence Berkeley Laboratories.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *may be used to endorse or promote products derived from this software
+ *without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED
[m5-dev] changeset in m5: SCons: Cleanup SCons output during compile
changeset 846fb3ffe0dc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=846fb3ffe0dc
description:
SCons: Cleanup SCons output during compile
diffstat:
SConstruct | 65 -
src/SConscript | 48 +++-
src/arch/SConscript| 3 +-
src/arch/isa_parser.py | 2 +-
src/cpu/SConscript | 2 +-
5 files changed, 82 insertions(+), 38 deletions(-)
diffs (truncated from 320 to 300 lines):
diff -r 5c374c1e0075 -r 846fb3ffe0dc SConstruct
--- a/SConstructMon Nov 15 14:04:03 2010 -0600
+++ b/SConstructMon Nov 15 14:04:04 2010 -0600
@@ -272,6 +272,7 @@
# Make sure build_root exists (might not if this is the first build there)
if not isdir(build_root):
mkdir(build_root)
+main['BUILDROOT'] = build_root
Export('main')
@@ -306,6 +307,7 @@
global_sticky_vars_file = joinpath(build_root, 'variables.global')
global_sticky_vars = Variables(global_sticky_vars_file, args=ARGUMENTS)
+global_nonsticky_vars = Variables(args=ARGUMENTS)
global_sticky_vars.AddVariables(
('CC', 'C compiler', environ.get('CC', main['CC'])),
@@ -317,6 +319,12 @@
PathListAllExist, PathListMakeAbsolute),
)
+global_nonsticky_vars.AddVariables(
+('VERBOSE', 'Print full tool command lines', False),
+('update_ref', 'Update test reference outputs', False)
+)
+
+
# base help text
help_text = '''
Usage: scons [scons options] [build options] [target(s)]
@@ -326,8 +334,10 @@
# Update main environment with values from ARGUMENTS global_sticky_vars_file
global_sticky_vars.Update(main)
+global_nonsticky_vars.Update(main)
help_text += global_sticky_vars.GenerateHelpText(main)
+help_text += global_nonsticky_vars.GenerateHelpText(main)
# Save sticky variable settings back to current variables file
global_sticky_vars.Save(global_sticky_vars_file, main)
@@ -346,6 +356,40 @@
# the ext directory should be on the #includes path
main.Append(CPPPATH=[Dir('ext')])
+def _STRIP(path, env):
+path = str(path)
+variant_base = env['BUILDROOT'] + os.path.sep
+if path.startswith(variant_base):
+path = path[len(variant_base):]
+elif path.startswith('build/'):
+path = path[6:]
+return path
+
+def _STRIP_SOURCE(target, source, env, for_signature):
+return _STRIP(source[0], env)
+main['STRIP_SOURCE'] = _STRIP_SOURCE
+
+def _STRIP_TARGET(target, source, env, for_signature):
+return _STRIP(target[0], env)
+main['STRIP_TARGET'] = _STRIP_TARGET
+
+if main['VERBOSE']:
+def MakeAction(action, string, *args, **kwargs):
+return Action(action, *args, **kwargs)
+else:
+MakeAction = Action
+main['CCCOMSTR']= ' [ CC] $STRIP_SOURCE'
+main['CXXCOMSTR'] = ' [ CXX] $STRIP_SOURCE'
+main['ASCOMSTR']= ' [ AS] $STRIP_SOURCE'
+main['SWIGCOMSTR'] = ' [SWIG] $STRIP_SOURCE'
+main['ARCOMSTR']= ' [ AR] $STRIP_TARGET'
+main['LINKCOMSTR'] = ' [LINK] $STRIP_TARGET'
+main['RANLIBCOMSTR']= ' [ RANLIB] $STRIP_TARGET'
+main['M4COMSTR']= ' [ M4] $STRIP_TARGET'
+main['SHCCCOMSTR'] = ' [SHCC] $STRIP_TARGET'
+main['SHCXXCOMSTR'] = ' [ SHCXX] $STRIP_TARGET'
+Export('MakeAction')
+
CXX_version = readCommand([main['CXX'],'--version'], exception=False)
CXX_V = readCommand([main['CXX'],'-V'], exception=False)
@@ -666,10 +710,6 @@
export_vars = []
Export('export_vars')
-# Non-sticky variables only apply to the current build.
-nonsticky_vars = Variables(args=ARGUMENTS)
-Export('nonsticky_vars')
-
# Walk the tree and execute all SConsopts scripts that wil add to the
# above variables
for bdir in [ base_dir ] + extras_dir_list:
@@ -706,10 +746,6 @@
BoolVariable('RUBY', 'Build with Ruby', False),
)
-nonsticky_vars.AddVariables(
-BoolVariable('update_ref', 'Update test reference outputs', False)
-)
-
# These variables get exported to #defines in config/*.hh (see src/SConscript).
export_vars += ['FULL_SYSTEM', 'USE_FENV', 'USE_MYSQL',
'NO_FAST_ALLOC', 'FAST_ALLOC_DEBUG', 'FAST_ALLOC_STATS',
@@ -787,15 +823,11 @@
print f, '#include %s/%s/%s' % (dname, isa, basename(fname))
f.close()
-# String to print when generating header
-def gen_switch_hdr_string(target, source, env):
-return Generating switch header + str(target[0])
-
# Build SCons Action object. 'varlist' specifies env vars that this
# action depends on; when env['ALL_ISA_LIST'] changes these actions
# should get re-executed.
-switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
- varlist=['ALL_ISA_LIST'])
+switch_hdr_action = MakeAction(gen_switch_hdr,
+ [GENERATE] $STRIP_TARGET, varlist=['ALL_ISA_LIST'])
# Instantiate actions for each header
for hdr in switch_headers:
@@ -852,12 +884,9 @@
[m5-dev] changeset in m5: O3: prevent a squash when completeAcc() modifie...
changeset 28a677d7cb51 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=28a677d7cb51
description:
O3: prevent a squash when completeAcc() modifies misc reg through TC.
This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc()
methods
diffstat:
src/cpu/o3/dyn_inst_impl.hh | 9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diffs (21 lines):
diff -r d7360f5052b2 -r 28a677d7cb51 src/cpu/o3/dyn_inst_impl.hh
--- a/src/cpu/o3/dyn_inst_impl.hh Mon Nov 15 14:04:04 2010 -0600
+++ b/src/cpu/o3/dyn_inst_impl.hh Mon Nov 15 14:04:04 2010 -0600
@@ -113,8 +113,17 @@
Fault
BaseO3DynInstImpl::completeAcc(PacketPtr pkt)
{
+// @todo: Pretty convoluted way to avoid squashing from happening
+// when using the TC during an instruction's execution
+// (specifically for instructions that have side-effects that use
+// the TC). Fix this.
+bool in_syscall = this-thread-inSyscall;
+this-thread-inSyscall = true;
+
this-fault = this-staticInst-completeAcc(pkt, this, this-traceData);
+this-thread-inSyscall = in_syscall;
+
return this-fault;
}
___
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[m5-dev] changeset in m5: CPU/ARM: Add SIMD op classes to CPU models and ...
changeset e93e7e0caae1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e93e7e0caae1
description:
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
diffstat:
src/arch/arm/isa/insts/div.isa |6 +-
src/arch/arm/isa/insts/fp.isa | 278 ++-
src/arch/arm/isa/insts/mult.isa |6 +-
src/arch/arm/isa/insts/neon.isa | 692 ---
src/cpu/FuncUnit.py | 17 +
src/cpu/o3/FUPool.py|2 +-
src/cpu/o3/FuncUnitConfig.py| 35 ++
src/cpu/op_class.hh | 32 +
8 files changed, 634 insertions(+), 434 deletions(-)
diffs (truncated from 2818 to 300 lines):
diff -r cf222bd91228 -r e93e7e0caae1 src/arch/arm/isa/insts/div.isa
--- a/src/arch/arm/isa/insts/div.isaMon Nov 15 14:04:04 2010 -0600
+++ b/src/arch/arm/isa/insts/div.isaMon Nov 15 14:04:04 2010 -0600
@@ -56,7 +56,8 @@
'''
sdivIop = InstObjParams(sdiv, Sdiv, RegRegRegOp,
{ code: sdivCode,
- predicate_test: predicateTest }, [])
+ predicate_test: predicateTest,
+ op_class: IntDivOp}, [])
header_output = RegRegRegOpDeclare.subst(sdivIop)
decoder_output = RegRegRegOpConstructor.subst(sdivIop)
exec_output = PredOpExecute.subst(sdivIop)
@@ -77,7 +78,8 @@
'''
udivIop = InstObjParams(udiv, Udiv, RegRegRegOp,
{ code: udivCode,
- predicate_test: predicateTest }, [])
+ predicate_test: predicateTest,
+ op_class: IntDivOp}, [])
header_output += RegRegRegOpDeclare.subst(udivIop)
decoder_output += RegRegRegOpConstructor.subst(udivIop)
exec_output += PredOpExecute.subst(udivIop)
diff -r cf222bd91228 -r e93e7e0caae1 src/arch/arm/isa/insts/fp.isa
--- a/src/arch/arm/isa/insts/fp.isa Mon Nov 15 14:04:04 2010 -0600
+++ b/src/arch/arm/isa/insts/fp.isa Mon Nov 15 14:04:04 2010 -0600
@@ -194,7 +194,8 @@
vmsrIop = InstObjParams(vmsr, Vmsr, FpRegRegOp,
{ code: vmsrEnabledCheckCode + \
MiscDest = Op1;,
- predicate_test: predicateTest },
+ predicate_test: predicateTest,
+ op_class: SimdFloatMiscOp },
[IsSerializeAfter,IsNonSpeculative])
header_output += FpRegRegOpDeclare.subst(vmsrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
@@ -206,15 +207,17 @@
'''
vmsrFpscrIop = InstObjParams(vmsr, VmsrFpscr, FpRegRegOp,
{ code: vmsrFpscrCode,
- predicate_test: predicateTest }, [])
+ predicate_test: predicateTest,
+ op_class: SimdFloatMiscOp }, [])
header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
exec_output += PredOpExecute.subst(vmsrFpscrIop);
vmrsIop = InstObjParams(vmrs, Vmrs, FpRegRegOp,
{ code: vmrsEnabledCheckCode + \
- Dest = MiscOp1;,
- predicate_test: predicateTest }, [])
+Dest = MiscOp1;,
+ predicate_test: predicateTest,
+ op_class: SimdFloatMiscOp }, [])
header_output += FpRegRegOpDeclare.subst(vmrsIop);
decoder_output += FpRegRegOpConstructor.subst(vmrsIop);
exec_output += PredOpExecute.subst(vmrsIop);
@@ -222,7 +225,8 @@
vmrsFpscrIop = InstObjParams(vmrs, VmrsFpscr, FpRegRegOp,
{ code: vmrsEnabledCheckCode + \
Dest = Fpscr | FpCondCodes;,
- predicate_test: predicateTest }, [])
+ predicate_test: predicateTest,
+ op_class: SimdFloatMiscOp }, [])
header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
exec_output += PredOpExecute.subst(vmrsFpscrIop);
@@ -232,7 +236,8 @@
'''
vmrsApsrIop = InstObjParams(vmrs, VmrsApsr, FpRegRegImmOp,
{ code: vmrsApsrCode,
- predicate_test: predicateTest }, [])
+ predicate_test: predicateTest,
+ op_class: SimdFloatMiscOp }, [])
header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
exec_output += PredOpExecute.subst(vmrsApsrIop);
@@ -243,7 +248,8 @@
'''
vmrsApsrFpscrIop = InstObjParams(vmrs, VmrsApsrFpscr,
[m5-dev] changeset in m5: ARM: Add comment about the organization of the ...
changeset 6e399e631a43 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6e399e631a43 description: ARM: Add comment about the organization of the IT state register diffstat: src/arch/arm/miscregs.hh | 6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diffs (16 lines): diff -r 50d219ed2a59 -r 6e399e631a43 src/arch/arm/miscregs.hh --- a/src/arch/arm/miscregs.hh Mon Nov 15 14:04:05 2010 -0600 +++ b/src/arch/arm/miscregs.hh Mon Nov 15 14:04:05 2010 -0600 @@ -262,6 +262,12 @@ EndBitUnion(CPSR) BitUnion8(ITSTATE) +/* Note that the split (cond, mask) below is not as in ARM ARM. + * But it is more convenient for simulation. The condition + * is always the concatenation of the top 3 bits and the next bit, + * which applies when one of the bottom 4 bits is set. + * Refer to predecoder.cc for the use case. + */ Bitfield7, 4 cond; Bitfield3, 0 mask; // Bitfields for moving to/from CPSR ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: O3: reset architetural state by calling clear()
changeset ff2213d13e58 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ff2213d13e58
description:
O3: reset architetural state by calling clear()
diffstat:
src/cpu/o3/thread_context_impl.hh | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diffs (31 lines):
diff -r 6e399e631a43 -r ff2213d13e58 src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/cpu/o3/thread_context_impl.hh Mon Nov 15 14:04:05 2010 -0600
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -257,7 +269,9 @@
template class Impl
void
O3ThreadContextImpl::clearArchRegs()
-{}
+{
+cpu-isa[thread-threadId()].clear();
+}
template class Impl
uint64_t
___
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Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.
On 2010-11-10 08:07:39, Steve Reinhardt wrote: So it looks like whether you call setMiscReg() or setMiscRegNoEffect() then you buffer the update and call setMiscReg() later... i.e., even if you called setMiscRegNoEffect() originally you end up calling setMiscReg() at commit. Are there ever cases where we call setMiscRegNoEffect() from an instruction? I thought it was strictly for things like system initialization and restoring from checkpoints anyway... maybe we don't need it in the ExecContext interface. Also, I see that these predate your change, but why do we need both the setMiscReg() calls and the setMiscRegOperand() calls? Is one of them deprecated? Can we take this opportunity to update the comments to distinguish them? We shouldn't have two different functions for which the descriptive comment is completely identical IMO. Ali Saidi wrote: You're right... The only place i can find an xc using setMiscRegNoEffect() is locked_mem.hh for alpha and what is the exact copy of it for MIPS. It seems like that could be setMiscReg(). The implementation for LOCKED_ADDR is identical (there are no effects). Perhaps we should remove it from the xc. My guess was that it was used with the intention of making it cheaper by not having the cpu squash when it happens, but in reality that didn't work out. The difference between the operand and no operand version is that the operand version gets the dest misc register from the instruction while the non-operand one expects it passed in as a parameter. One should be implemented in terms of the other, but both seem to be used. Gabe Black wrote: Yeah, I think generally setMiscRegOperand is going to be called from generated code and setMiscReg is going to be used by handwritten code where the index is provided directly. Ok... I removed the NoEffect versions from the exec context and changed the *Operand versions to just call their non-operand versions which cleans up the code some. Alpha has no problem with these changes, but they do uncover a bug with SPARC that somehow worked, but it's amazing that it did. The ASI register changes the type of instruction that is executing (e.g. one ASI is a type of prefetch vs. load vs. load with a different addressing mode etc). The types are decoded from the ASI bits in the ExtMachInst which are inserted by the pre-decoder. The trouble is that these bits are inserted in fetch which is before rename so the IsSerializing flags don't prevent it from happening. Thus, while the wrasi instruction can be marked as Serializing fetch already has read the old value and created the instructions based on the old ASI. When wrasi commits the old instructions flow through the rest of the pipeline and that isn't great. It's amazing that all the code sequences that Gabe used to run on the sparc/o3 model never ran into this issue. With the current code if you executed a alternating wrasi and load w/asi instructions you would get some very odd results. Anyway, the question becomes how do we fix this??? My current solution is to add an instruction flag that after commit flushes the CPU. Although, I don't know if this is enough and what other surprises I'll run into. Thoughts? Ali - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/298/#review473 --- On 2010-11-08 15:46:52, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/298/ --- (Updated 2010-11-08 15:46:52) Review request for Default. Summary --- O3: Make all instructions that write a misc register not perform the write until commit. ARM Instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Diffs - src/arch/arm/isa.cc f61e079ad05e src/arch/arm/isa/insts/fp.isa f61e079ad05e src/arch/arm/isa/insts/neon.isa f61e079ad05e src/arch/arm/isa/operands.isa f61e079ad05e src/arch/arm/miscregs.hh f61e079ad05e src/cpu/o3/commit_impl.hh f61e079ad05e src/cpu/o3/dyn_inst.hh f61e079ad05e src/cpu/o3/dyn_inst_impl.hh f61e079ad05e Diff: http://reviews.m5sim.org/r/298/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.
On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote: It seems like our notion of serializing came from the definition Alpha uses, and sometimes we need a stronger one. X86 is going to have similar issues in some cases, although I couldn't necessarily list them for you off hand. The nuke everything flag your proposing might be the best solution because I doubt we'd ever need anything stronger than that. Maybe you could make the CPU stop fetching too, but I don't see how that would be useful and it's probably very hard to do. This also highlights the usefulness of target tests of particular features like changing the ISA and then immediately using it as apposed to getting specific workloads to work. The compiler, code author, etc., only wants to achieve a functional result, and they'll probably use the same structure and features over and over again since those work well, are equivalently good to the other options, etc. There are swathes of x86, which granted is very large, that aren't implemented at all and Linux boots just fine, but depending on how picky you are you could say those areas are severely broken. The same thing could be happening less intentionally elsewhere. I don't mean to pick on you Gabe, I'm just surprised that when the compiler inserts wr asi in happens to also include enough padding before it needs it that it worked in the past. I think the load that used it would minimally have to be a cache line away. It's just bizarre to me unless there was an interlock on wr asi that they knew about. Anyway, I've added a flag called isSquashState. I don't like the name, so please propose a better one. isSquashAfter? After commit in the o3 cpu it checks for the flag and squashes the world. This clears up the issue enough for gzip to start running. I should know in 3 hours if it is sufficient. Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.
Quoting Ali Saidi sa...@umich.edu: On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote: It seems like our notion of serializing came from the definition Alpha uses, and sometimes we need a stronger one. X86 is going to have similar issues in some cases, although I couldn't necessarily list them for you off hand. The nuke everything flag your proposing might be the best solution because I doubt we'd ever need anything stronger than that. Maybe you could make the CPU stop fetching too, but I don't see how that would be useful and it's probably very hard to do. This also highlights the usefulness of target tests of particular features like changing the ISA and then immediately using it as apposed to getting specific workloads to work. The compiler, code author, etc., only wants to achieve a functional result, and they'll probably use the same structure and features over and over again since those work well, are equivalently good to the other options, etc. There are swathes of x86, which granted is very large, that aren't implemented at all and Linux boots just fine, but depending on how picky you are you could say those areas are severely broken. The same thing could be happening less intentionally elsewhere. I don't mean to pick on you Gabe, I'm just surprised that when the compiler inserts wr asi in happens to also include enough padding before it needs it that it worked in the past. I think the load that used it would minimally have to be a cache line away. It's just bizarre to me unless there was an interlock on wr asi that they knew about. Anyway, I've added a flag called isSquashState. I don't like the name, so please propose a better one. isSquashAfter? After commit in the o3 cpu it checks for the flag and squashes the world. This clears up the issue enough for gzip to start running. I should know in 3 hours if it is sufficient. Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev No problem, I didn't think you were picking on me :-). Weren't there fake faults introduced to ARM that were used for a similar effect? The flag approach is better I think, but the instructions that throw that fault could be refitted, right? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.
On Nov 15, 2010, at 8:44 PM, Gabriel Michael Black wrote: Quoting Ali Saidi sa...@umich.edu: On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote: It seems like our notion of serializing came from the definition Alpha uses, and sometimes we need a stronger one. X86 is going to have similar issues in some cases, although I couldn't necessarily list them for you off hand. The nuke everything flag your proposing might be the best solution because I doubt we'd ever need anything stronger than that. Maybe you could make the CPU stop fetching too, but I don't see how that would be useful and it's probably very hard to do. This also highlights the usefulness of target tests of particular features like changing the ISA and then immediately using it as apposed to getting specific workloads to work. The compiler, code author, etc., only wants to achieve a functional result, and they'll probably use the same structure and features over and over again since those work well, are equivalently good to the other options, etc. There are swathes of x86, which granted is very large, that aren't implemented at all and Linux boots just fine, but depending on how picky you are you could say those areas are severely broken. The same thing could be happening less intentionally elsewhere. I don't mean to pick on you Gabe, I'm just surprised that when the compiler inserts wr asi in happens to also include enough padding before it needs it that it worked in the past. I think the load that used it would minimally have to be a cache line away. It's just bizarre to me unless there was an interlock on wr asi that they knew about. Anyway, I've added a flag called isSquashState. I don't like the name, so please propose a better one. isSquashAfter? After commit in the o3 cpu it checks for the flag and squashes the world. This clears up the issue enough for gzip to start running. I should know in 3 hours if it is sufficient. Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev No problem, I didn't think you were picking on me :-). Weren't there fake faults introduced to ARM that were used for a similar effect? The flag approach is better I think, but the instructions that throw that fault could be refitted, right? The fault is another level that is even more strict. The fault requires the store queue to completely drain before continuing, while this doesn't. Retrofitting it wouldn't be enough and perhaps there are three levels. Stall rename, squash and refetch, and squash, refetch, and drain. Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: O3: Make O3 support variably lengthed instructi...
changeset 03efcdc3421f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=03efcdc3421f
description:
O3: Make O3 support variably lengthed instructions.
diffstat:
src/arch/alpha/predecoder.hh | 11 +-
src/arch/mips/predecoder.hh | 11 +-
src/arch/power/predecoder.hh |8 +-
src/arch/sparc/predecoder.hh | 13 +-
src/cpu/base.hh |3 +
src/cpu/o3/fetch.hh | 13 +-
src/cpu/o3/fetch_impl.hh | 272 +++---
src/cpu/simple/base.hh |3 -
8 files changed, 196 insertions(+), 138 deletions(-)
diffs (truncated from 689 to 300 lines):
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/alpha/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -47,10 +47,11 @@
// The extended machine instruction being generated
ExtMachInst ext_inst;
+bool emiIsReady;
public:
Predecoder(ThreadContext * _tc)
-: tc(_tc)
+: tc(_tc), emiIsReady(false)
{}
ThreadContext *
@@ -71,7 +72,9 @@
void
reset()
-{ }
+{
+emiIsReady = false;
+}
// Use this to give data to the predecoder. This should be used
// when there is control flow.
@@ -79,6 +82,7 @@
moreBytes(const PCState pc, Addr fetchPC, MachInst inst)
{
ext_inst = inst;
+emiIsReady = true;
#if FULL_SYSTEM
ext_inst |= (static_castExtMachInst(pc.pc() 0x1) 32);
#endif
@@ -93,13 +97,14 @@
bool
extMachInstReady()
{
-return true;
+return emiIsReady;
}
// This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst
getExtMachInst(PCState pc)
{
+emiIsReady = false;
return ext_inst;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/mips/predecoder.hh
--- a/src/arch/mips/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/mips/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -47,9 +47,10 @@
ThreadContext * tc;
//The extended machine instruction being generated
ExtMachInst emi;
+bool emiIsReady;
public:
-Predecoder(ThreadContext * _tc) : tc(_tc)
+Predecoder(ThreadContext * _tc) : tc(_tc), emiIsReady(false)
{}
ThreadContext *getTC()
@@ -70,7 +71,9 @@
void
reset()
-{}
+{
+emiIsReady = false;
+}
//Use this to give data to the predecoder. This should be used
//when there is control flow.
@@ -78,6 +81,7 @@
moreBytes(const PCState pc, Addr fetchPC, MachInst inst)
{
emi = inst;
+emiIsReady = true;
}
bool
@@ -89,13 +93,14 @@
bool
extMachInstReady()
{
-return true;
+return emiIsReady;
}
//This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst
getExtMachInst(PCState pc)
{
+emiIsReady = false;
return emi;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/power/predecoder.hh
--- a/src/arch/power/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/power/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -51,10 +51,11 @@
// The extended machine instruction being generated
ExtMachInst emi;
+bool emiIsReady;
public:
Predecoder(ThreadContext * _tc)
-: tc(_tc)
+: tc(_tc), emiIsReady(false)
{
}
@@ -78,6 +79,7 @@
void
reset()
{
+emiIsReady = false;
}
// Use this to give data to the predecoder. This should be used
@@ -86,6 +88,7 @@
moreBytes(const PCState pc, Addr fetchPC, MachInst inst)
{
emi = inst;
+emiIsReady = true;
}
// Use this to give data to the predecoder. This should be used
@@ -105,13 +108,14 @@
bool
extMachInstReady()
{
-return true;
+return emiIsReady;
}
// This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst
getExtMachInst(PCState pcState)
{
+emiIsReady = false;
return emi;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/sparc/predecoder.hh
--- a/src/arch/sparc/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/sparc/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -49,9 +49,10 @@
ThreadContext * tc;
// The extended machine instruction being generated
ExtMachInst emi;
+bool emiIsReady;
public:
-Predecoder(ThreadContext * _tc) : tc(_tc)
+Predecoder(ThreadContext * _tc) : tc(_tc), emiIsReady(false)
{}
ThreadContext *
@@ -67,7 +68,11 @@
}
void process() {}
-void reset() {}
+void
+reset()
+{
+emiIsReady = false;
+}
// Use this to give data to the predecoder. This should be used
// when there is control flow.
@@ -87,6 +92,7 @@
[m5-dev] changeset in m5: Stats: Update the O3 fetch stats for SPARC.
changeset 634d88f0dbd4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=634d88f0dbd4 description: Stats: Update the O3 fetch stats for SPARC. diffstat: tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diffs (18 lines): diff -r 03efcdc3421f -r 634d88f0dbd4 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txtMon Nov 15 19:37:03 2010 -0800 +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txtMon Nov 15 19:37:15 2010 -0800 @@ -136,12 +136,12 @@ system.cpu.fetch.CacheLines 173095521 # Number of cache lines fetched system.cpu.fetch.Cycles 548231197 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 1429406 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1760522570 # Number of instructions fetch has processed +system.cpu.fetch.Insts 1755969057 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 6170035 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 173095521 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 98804348 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate1.463554 # Number of inst fetches per cycle +system.cpu.fetch.rate1.459768 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 1202543536 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.699989 # Number of instructions fetched each cycle (Total) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller
On 11/15/10 12:09, Ali Saidi wrote: diffs (119 lines): diff -r 859e8bc1cdc2 -r 0731d632db76 configs/common/FSConfig.py --- a/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 +++ b/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 @@ -209,6 +209,16 @@ self.mem_mode = mem_mode +#self.cf0 = CowIdeDisk(driveID='master') +#self.cf0.childImage(mdesc.disk()) +#self.cf_ctrl = IdeController(disks=[self.cf0], +# pci_func = 0, pci_dev = 0, pci_bus = 0, +# io_shift = 1, ctrl_offset = 2, Command = 0x1, +# BAR0 = 0x1800, BAR0Size = '16B', +# BAR1 = 0x18000100, BAR1Size = '1B', +# BAR0LegacyIO = True, BAR1LegacyIO = True,) +#self.cf_ctrl.pio = self.iobus.port + if machine_type == RealView_PBX: self.realview = RealViewPBX() elif machine_type == RealView_EB: Should these lines have been deleted or uncommented? I assume one or the other. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller
On Nov 15, 2010, at 9:52 PM, Gabe Black wrote: On 11/15/10 12:09, Ali Saidi wrote: diffs (119 lines): diff -r 859e8bc1cdc2 -r 0731d632db76 configs/common/FSConfig.py --- a/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 +++ b/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 @@ -209,6 +209,16 @@ self.mem_mode = mem_mode +#self.cf0 = CowIdeDisk(driveID='master') +#self.cf0.childImage(mdesc.disk()) +#self.cf_ctrl = IdeController(disks=[self.cf0], +# pci_func = 0, pci_dev = 0, pci_bus = 0, +# io_shift = 1, ctrl_offset = 2, Command = 0x1, +# BAR0 = 0x1800, BAR0Size = '16B', +# BAR1 = 0x18000100, BAR1Size = '1B', +# BAR0LegacyIO = True, BAR1LegacyIO = True,) +#self.cf_ctrl.pio = self.iobus.port + if machine_type == RealView_PBX: self.realview = RealViewPBX() elif machine_type == RealView_EB: Should these lines have been deleted or uncommented? I assume one or the other. It was intentional. I didn't want to enable it yet and adding it effects the stats, however I also didn't want to have to figure out the addresses and such again. It will get uncommented soon. Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: ARM: Take advantage of new PCState syntax.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/#review483 --- src/arch/arm/isa/operands.isa http://reviews.m5sim.org/r/312/#comment698 Ok, I thought I commented on this last time. This is nuts. You can't have this random number here that needs to change whenever you do something. - Nathan On 2010-11-15 04:28:11, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/ --- (Updated 2010-11-15 04:28:11) Review request for Default. Summary --- ARM: Take advantage of new PCState syntax. Diffs - src/arch/arm/isa/insts/branch.isa f440cdaf1c2d src/arch/arm/isa/insts/data.isa f440cdaf1c2d src/arch/arm/isa/insts/ldr.isa f440cdaf1c2d src/arch/arm/isa/insts/macromem.isa f440cdaf1c2d src/arch/arm/isa/insts/misc.isa f440cdaf1c2d src/arch/arm/isa/operands.isa f440cdaf1c2d Diff: http://reviews.m5sim.org/r/312/diff Testing --- Thanks, Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: imported patch ext/noisa.patch
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/303/#review484 --- Ship it! I can't wait to use it - Nathan On 2010-11-15 14:43:46, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/303/ --- (Updated 2010-11-15 14:43:46) Review request for Default. Summary --- imported patch ext/noisa.patch Diffs - build_opts/NOISA PRE-CREATION src/arch/noisa/SConsopts PRE-CREATION src/arch/noisa/cpu_dummy.hh PRE-CREATION src/base/SConscript ff2213d13e58 src/cpu/SConscript ff2213d13e58 src/cpu/nocpu/SConsopts PRE-CREATION src/dev/SConscript ff2213d13e58 src/kern/SConscript ff2213d13e58 src/mem/SConscript ff2213d13e58 src/mem/cache/SConscript ff2213d13e58 src/mem/cache/prefetch/SConscript ff2213d13e58 src/mem/cache/tags/SConscript ff2213d13e58 src/mem/ruby/SConscript ff2213d13e58 src/python/swig/pyobject.hh ff2213d13e58 src/sim/SConscript ff2213d13e58 src/sim/stat_control.cc ff2213d13e58 src/unittest/SConscript ff2213d13e58 Diff: http://reviews.m5sim.org/r/303/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: imported patch ext/noisa.patch
Think I could convince you to get your stats changes in order. :) Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
