* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
*
It seems that this will work out. We can make AbstractController call a
static function of RubyPort class that will add the calling object to some
list which will be accessed while making functional accesses. As far as
pushing functional access support to Sequencer in to concerned, there was
Sorry I missed this thread... I just read Nilay's response about python
issues and he pointed me over here.
One thing we should think about is that we really only want the caches
within a single system to be flushed at once... I know that it's unlikely
that anyone will want to model two systems
Forgot to mention that this is how we handle registering all the thread
contexts within a system... you can look at that code (in the CPU models and
in System) for an example.
On Tue, Mar 8, 2011 at 7:16 AM, Steve Reinhardt ste...@gmail.com wrote:
Sorry I missed this thread... I just read
Great. It sounds like we are thinking of a similar solution. Just one thing I
want to point out is AbstractController may not be the right place to build the
list. As you know, sometimes a controller may manage multiple cachememory
objects and other controllers may not manage any cachememory
Hi Nilay,
It looks like my email filter of the m5-dev list cause me to basically send you
the same suggestion that Steve sent you. Sorry for the confusion, but it is
good to know that Steve and I at least are considering the same problem. From
now on, let's drop our individual email
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Hi Somayeh,
I have several comments and questions that pertain to both
When does the following error occurs? Is it that an object is being
accessed while it is being created?
File
/afs/cs.wisc.edu/u/n/i/nilay/private/Architecture/GEM5/m5/src/python/m5/SimObject.py,
line 834, in getCCObject
raise RuntimeError, %s: Cycle found in configuration hierarchy. \
It probably means that two objects have pointers to each other as parameters
(or more generally there's a cycle). See step 3 here:
http://m5sim.org/wiki/index.php/SimObject_Initialization
On Tue, Mar 8, 2011 at 4:27 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
When does the following error
On 2011-03-08 11:53:38, Brad Beckmann wrote:
src/mem/protocol/MOESI_hammer-cache.sm, line 1096
http://reviews.m5sim.org/r/552/diff/1/?file=10718#file10718line1096
Is there a reason why you need this action and the vt_ action for
writing the tbe versus using the pre-existing
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Review request for Default and Brad Beckmann.
Summary
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MOESI_hammer: cache
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Review request for Default and Brad Beckmann.
Summary
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MOESI_hammer: cache
Somayeh, there is an update option available in postreview. I think it is
-u request number. You can use that to post update already created
review requests.
--
Nilay
On Wed, 9 Mar 2011, Somayeh Sardashti wrote:
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This is an
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