[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

scons: *** Found dependency cycle(s): * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. *

Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

On Sat, March 19, 2011 3:26 am, Cron Daemon wrote: scons: *** Found dependency cycle(s): I am looking at the output of the regression from last night. What do the following errors mean? scons: *** Found dependency cycle(s): Internal Error: no cycle found for node

Re: [m5-dev] Review Request: Ruby: Convert CacheRequestType to RubyRequestType

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/602/#review995 --- Ship it! - Brad On 2011-03-18 21:55:58, Nilay Vaish wrote:

Re: [m5-dev] Review Request: Ruby: Convert AccessModeType to RubyAccessMode

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/601/#review996 --- Ship it! - Brad On 2011-03-18 21:55:08, Nilay Vaish wrote:

[m5-dev] changeset in m5: MOESI_CMP_directory: significant dma bug fixes

changeset d2cf4b19e8ad in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d2cf4b19e8ad description: MOESI_CMP_directory: significant dma bug fixes diffstat: src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 67 - src/mem/protocol/MOESI_CMP_directory-L2cache.sm

[m5-dev] changeset in m5: MOESI_hammer: fixed dma bug with shared data

changeset 519fba665871 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=519fba665871 description: MOESI_hammer: fixed dma bug with shared data diffstat: src/mem/protocol/MOESI_hammer-cache.sm | 35 + src/mem/protocol/MOESI_hammer-dir.sm

[m5-dev] changeset in m5: slicc: improved invalid transition message

changeset de9e34de70ff in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=de9e34de70ff description: slicc: improved invalid transition message diffstat: src/mem/slicc/symbols/StateMachine.py | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diffs (14 lines):

[m5-dev] changeset in m5: ruby: added useful dma progress dprintf

changeset 0b3252d3b400 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0b3252d3b400 description: ruby: added useful dma progress dprintf diffstat: src/mem/ruby/system/DMASequencer.cc | 5 - 1 files changed, 4 insertions(+), 1 deletions(-) diffs (15 lines): diff

[m5-dev] changeset in m5: RubyPort: minor fixes to trace flag and dprintfs

changeset ebb373fcb206 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ebb373fcb206 description: RubyPort: minor fixes to trace flag and dprintfs diffstat: src/mem/SConscript | 4 ++-- src/mem/ruby/system/RubyPort.cc | 30 +++---

[m5-dev] changeset in m5: Ruby: dma retry fix

changeset 5f69f1b0039e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=5f69f1b0039e description: Ruby: dma retry fix This patch fixes the problem where Ruby would fail to call sendRetry on ports after it nacked the port. This patch is particularly

[m5-dev] changeset in m5: MOESI_hammer: minor fixes to full-bit dir

changeset 19a654839a04 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=19a654839a04 description: MOESI_hammer: minor fixes to full-bit dir diffstat: src/mem/protocol/MOESI_hammer-dir.sm | 8 +--- 1 files changed, 5 insertions(+), 3 deletions(-) diffs (39 lines):

Re: [m5-dev] Review Request: configs: combine ruby_se.py and se.py to avoid all that code duplication

On 2011-03-18 18:17:54, Gabe Black wrote: configs/example/se.py, line 160 http://reviews.m5sim.org/r/600/diff/1/?file=11047#file11047line160 I applaud getting rid of the duplication, but isn't it a little dangerous here to set up a fake TimingSimpleCPU class and to ignore the

Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

On 2011-03-18 18:30:07, Gabe Black wrote: configs/example/se.py, line 83 http://reviews.m5sim.org/r/598/diff/1/?file=11044#file11044line83 Splitting on , would be a little more standard. True. I have a moderately good reason for this. When creating an aggregated checkpoint, the

Re: [m5-dev] Review Request: enable x86 workloads on se.py

On 2011-03-18 16:50:14, Ali Saidi wrote: configs/example/se.py, line 92 http://reviews.m5sim.org/r/599/diff/1/?file=11045#file11045line92 Why not just change this to exec(workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref') % app) ? I realize that alpha is a special case with

[m5-dev] changeset in m5: Ruby: Convert AccessModeType to RubyAccessMode

changeset b043c0efa024 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b043c0efa024 description: Ruby: Convert AccessModeType to RubyAccessMode This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code

[m5-dev] changeset in m5: Ruby: Convert CacheRequestType to RubyRequestType

changeset 5955406f7ed0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=5955406f7ed0 description: Ruby: Convert CacheRequestType to RubyRequestType This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent

[m5-dev] changeset in m5: se.py: Modify script to make multiprogramming m...

changeset f596091c854d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f596091c854d description: se.py: Modify script to make multiprogramming much easier. Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will set up a

[m5-dev] changeset in m5: enable x86 workloads on se.py

changeset 5cbb0a68dce1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=5cbb0a68dce1 description: enable x86 workloads on se.py diffstat: configs/example/se.py | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diffs (22 lines): diff -r f596091c854d

[m5-dev] changeset in m5: configs: combine ruby_se.py and se.py to avoid ...

changeset 89cd8302abd3 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=89cd8302abd3 description: configs: combine ruby_se.py and se.py to avoid all that code duplication diffstat: configs/example/ruby_se.py | 170 -

Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

On 2011-03-18 18:30:07, Gabe Black wrote: configs/example/se.py, line 83 http://reviews.m5sim.org/r/598/diff/1/?file=11044#file11044line83 Splitting on , would be a little more standard. Lisa Hsu wrote: True. I have a moderately good reason for this. When creating an