[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-03-30 Thread Cron Daemon
scons: *** Source `tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt' not found, needed by target `build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing/status'. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. *

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/520/ --- (Updated 2011-03-30 08:41:48.614227) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/520/#review1033 --- I think the updated patch addresses all of your issues Gabe. I tested it

Re: [m5-dev] Review Request: cpu: split o3-specific parts out of BaseDynInst

2011-03-30 Thread Korey Sewell
On 2011-03-29 10:02:01, Gabe Black wrote: I agree with the sentiment of this change, but I think you moved too much into the O3 class. There's functionality (pointed out below) that you'll need to support in InOrder to be compliant with the interface instructions expect from CPUs,

[m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/612/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-03-30 Thread Steve Reinhardt
We've had multiple discussions on this (search the list archives for m5-stable and you should find them). We had some debate about how frequently m5-stable should be updated, and how long we want a changeset to mature in m5 before we consider promoting it to m5-stable, but I think we found some

[m5-dev] Review Request: ARM: Tag appropriate instructions as IsReturn

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/614/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: ARM: Cleanup implementation of ITSTATE and put important code in PCState.

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/616/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: ARM: Fix table walk going on while ASID changes error

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/617/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/520/#review1034 --- I can't verify 100% that the code in your new function is correct, but I

Re: [m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/612/#review1035 --- Looks good to me. - Gabe On 2011-03-30 08:58:56, Ali Saidi wrote:

Re: [m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Gabe Black
This does interact with Korey's change a bit, so hopefully we don't end up stepping on each other too much. Since somebody's going to have to update a patch anyway, I'll look at whether that result stuff in the dyninst can go away too. Gabe On 03/30/11 12:09, Gabe Black wrote:

Re: [m5-dev] Review Request: ARM: Tag appropriate instructions as IsReturn

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/614/#review1036 --- One thing that should change is that isBranch passes through the ISA

Re: [m5-dev] Review Request: ARM: Fix table walk going on while ASID changes error

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/617/#review1037 --- src/arch/arm/faults.cc http://reviews.m5sim.org/r/617/#comment1408

Re: [m5-dev] Review Request: ARM: Cleanup implementation of ITSTATE and put important code in PCState.

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/616/#review1038 --- This is a great change. I saw one style mistake, and also I think some

Re: [m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Gabe Black
They're used in Checker and Ozone (and orthogonally overloaded in InOrder it looks like). Checker and Ozone really need to be either updated and disposed of, but until that happens I suppose it doesn't make sense to make it worse -and- complicate these other two patches by getting rid of the

Re: [m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Gabe Black
updated -or- disposed of. One is sufficient :-). Gabe On 03/30/11 13:13, Gabe Black wrote: They're used in Checker and Ozone (and orthogonally overloaded in InOrder it looks like). Checker and Ozone really need to be either updated and disposed of, but until that happens I suppose it doesn't

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-03-30 Thread Ali Saidi
On 2011-03-30 09:08:07, Gabe Black wrote: src/cpu/base_dyn_inst.hh, line 246 http://reviews.m5sim.org/r/520/diff/2/?file=11291#file11291line246 This comment is inaccurate. It's really the largest address that's part of the request, which is the effective address plus the size and

Re: [m5-dev] Review Request: ARM: Tag appropriate instructions as IsReturn

2011-03-30 Thread Ali Saidi
On 2011-03-30 09:22:13, Gabe Black wrote: One thing that should change is that isBranch passes through the ISA description code and fills in the template with the same value every time. If it's always the same (or could be harmlessly) then it should just be in the template. Note that

Re: [m5-dev] Review Request: ARM: Fix table walk going on while ASID changes error

2011-03-30 Thread Ali Saidi
On 2011-03-30 09:29:31, Gabe Black wrote: src/arch/arm/table_walker.cc, line 128 http://reviews.m5sim.org/r/617/diff/1/?file=11356#file11356line128 This panic doesn't do anything any more. it does still catch some cases. - Ali

Re: [m5-dev] Review Request: ARM: Fix table walk going on while ASID changes error

2011-03-30 Thread Ali Saidi
On 2011-03-30 09:29:31, Gabe Black wrote: src/arch/arm/faults.cc, line 233 http://reviews.m5sim.org/r/617/diff/1/?file=11355#file11355line233 The Faults trace flag can be useful during boot to see where things go haywire since early on there shouldn't be any, at least in ISAs

Re: [m5-dev] Review Request: ARM: Cleanup implementation of ITSTATE and put important code in PCState.

2011-03-30 Thread Ali Saidi
On 2011-03-30 09:53:54, Gabe Black wrote: src/arch/arm/types.hh, line 350 http://reviews.m5sim.org/r/616/diff/1/?file=11348#file11348line350 You could add new fields to the ITSTATE bitunion that would make this easier. cond and mask could be SubBitUnions which can be treated as

Re: [m5-dev] Review Request: ARM: Tag appropriate instructions as IsReturn

2011-03-30 Thread Gabe Black
On 2011-03-30 09:22:13, Gabe Black wrote: One thing that should change is that isBranch passes through the ISA description code and fills in the template with the same value every time. If it's always the same (or could be harmlessly) then it should just be in the template. Note that

Re: [m5-dev] Review Request: ARM: Fix table walk going on while ASID changes error

2011-03-30 Thread Gabe Black
On 2011-03-30 09:29:31, Gabe Black wrote: src/arch/arm/table_walker.cc, line 128 http://reviews.m5sim.org/r/617/diff/1/?file=11356#file11356line128 This panic doesn't do anything any more. Ali Saidi wrote: it does still catch some cases. Oh, yeah. Duh :-P. On 2011-03-30

Re: [m5-dev] Review Request: ARM: Cleanup implementation of ITSTATE and put important code in PCState.

2011-03-30 Thread Gabe Black
On 2011-03-30 09:53:54, Gabe Black wrote: src/arch/arm/types.hh, line 350 http://reviews.m5sim.org/r/616/diff/1/?file=11348#file11348line350 You could add new fields to the ITSTATE bitunion that would make this easier. cond and mask could be SubBitUnions which can be treated as

[m5-dev] Ruby Optimization Opportunity?

2011-03-30 Thread Korey Sewell
Hi all, I had noticed that Ruby was running a little slower than the old M5 memory system and decided to run gprof on it to see if there was anything obvious holding things up. For 2, 4, and 8 core ALPHA_FS_MOESI_CMP_directory, SimpleCPU runs for the Fft benchmark, it seems that the

[m5-dev] Review Request: ARM: Fix m5op parameters bug.

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/618/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

2011-03-30 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/620/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: ARM: Fix m5op parameters bug.

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/618/#review1047 --- LGTM - Gabe On 2011-03-30 14:53:40, Ali Saidi wrote:

Re: [m5-dev] Review Request: ARM: Fix bug in MicroLdrNeon templates for initiateAcc().

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/619/#review1048 --- Looks mostly good. src/arch/arm/isa/templates/mem.isa

Re: [m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

2011-03-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/620/#review1049 --- I'm not sure this is right yet. Won't it only copy the USR registers now

Re: [m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

2011-03-30 Thread Ali Saidi
On 2011-03-30 15:38:14, Gabe Black wrote: I'm not sure this is right yet. Won't it only copy the USR registers now and leave out all the other modes? Also, is there anything wrong with reading the CPSR, changing the mode, and then writing it back? No, NumIntRegs is all the registers in

Re: [m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

2011-03-30 Thread Gabe Black
On 2011-03-30 15:38:14, Gabe Black wrote: I'm not sure this is right yet. Won't it only copy the USR registers now and leave out all the other modes? Also, is there anything wrong with reading the CPSR, changing the mode, and then writing it back? Ali Saidi wrote: No, NumIntRegs

Re: [m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

2011-03-30 Thread Ali Saidi
On 2011-03-30 15:38:14, Gabe Black wrote: I'm not sure this is right yet. Won't it only copy the USR registers now and leave out all the other modes? Also, is there anything wrong with reading the CPSR, changing the mode, and then writing it back? Ali Saidi wrote: No, NumIntRegs

Re: [m5-dev] Review Request: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

2011-03-30 Thread Gabe Black
On 2011-03-30 15:38:14, Gabe Black wrote: I'm not sure this is right yet. Won't it only copy the USR registers now and leave out all the other modes? Also, is there anything wrong with reading the CPSR, changing the mode, and then writing it back? Ali Saidi wrote: No, NumIntRegs

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

2011-03-30 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/ --- (Updated 2011-03-30 16:19:26.551926) Review request for Default. Summary ---

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

2011-03-30 Thread Nilay Vaish
On Tue, 29 Mar 2011, Nilay Vaish wrote: Brad, I have posted on the review board my current implementation for supporting functional accesses in Ruby. This is untested and is mainly meant for furthering the discussions. I have some questions for you -- 1. How do we inform the other end of

Re: [m5-dev] Running Ruby w/32 Cores

2011-03-30 Thread Lisa Hsu
I think you forgot the attachments :P. Sometimes, if ProtocolTrace isn't enough for me to find a problem, I turn on RubySlicc and RubyGenerated as well. RubySlicc is the DPRINTFs within the actual protocol *.sm files, and RubyGenerated are inside of the generated code that you will only see in

Re: [m5-dev] Ruby Store/Coaslescing Buffer Implementation for TimingSimpleCPU

2011-03-30 Thread Lisa Hsu
Malek, TimingSimpleCPUs are in-order CPU models and only do one instruction at a time, so coalescing at the CPU won't make any sense, since there will be nothing to coalesce. Unless you want to do your coalescing further down the memory hierarchy where you might have multiple accesses from

Re: [m5-dev] Ruby Optimization Opportunity?

2011-03-30 Thread Nilay Vaish
Korey, I do not have the FftBase32 benchmark. Is it possible for you to run the simulation with one of the following benchmarks -- IScsiInitiator, IScsiTarget, MutexTest, NetperfMaerts, NetperfStream, NetperfStreamNT, NetperfStreamUdp, NetperfUdpLocal, Nfs, NfsTcp, Nhfsstone, Ping,

Re: [m5-dev] Ruby Question about MESI_CMP and implications of a Blocking Protocol

2011-03-30 Thread Lisa Hsu
Hi Malek, I think the term blocking is confusing because it's really an overloaded term. There's a distinction is between blocking CPUs and blocking memory systems, and they are distinct. As you say below, a TimingCPU is a blocking CPU and only has one outstanding instruction going at a time.

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

2011-03-30 Thread Beckmann, Brad
Hi Nilay, Thanks for posting a new patch. I will review it as soon as I can...hopefully tonight. Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Nilay Vaish Sent: Wednesday, March 30, 2011 4:32 PM To: Default Subject: Re:

Re: [m5-dev] Running Ruby w/32 Cores

2011-03-30 Thread Beckmann, Brad
Hi Korey, For the first trace, it looks like the L2 cache is either miscounting the number of valid L1 copies, or there is an error with the ack arithmetic. We are going to need a bit more information to figure out where the exact problem is. Could you apply the attached patch and reply with