[m5-dev] Files

Hi all, Can you please tell me where is the file "enums/OpClass.hh" included in "src/cpu/op_class.hh"? Thank you. Best, KJ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: debug: fix help output

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[m5-dev] changeset in m5: regress: updates after changing ruby network ba...

changeset dba41dbef071 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=dba41dbef071 description: regress: updates after changing ruby network bandwidth diffstat: tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini |76 +- tests

[m5-dev] changeset in m5: garnet: removed flit_width from Routers

changeset 89d0e7c17d1e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=89d0e7c17d1e description: garnet: removed flit_width from Routers diffstat: src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py | 1 - src/mem/ruby/network/garnet/fixed-pipeline/Router_d.

[m5-dev] changeset in m5: network: set the ExtLink bw to 16 bytes

changeset 8743998edfd3 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=8743998edfd3 description: network: set the ExtLink bw to 16 bytes Therefore all links by default are 16 bytes wide and thus work with Garnet's uniform link bandwidth assumption. diff

[m5-dev] changeset in m5: network: adjusted default endpoint bandwidth

changeset 39e42ccddd63 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=39e42ccddd63 description: network: adjusted default endpoint bandwidth The simple network's endpoint bandwidth value is used to adjust the overall bandwidth of the network. Specifica

[m5-dev] changeset in m5: network: moved network config params

changeset 36987780169e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=36987780169e description: network: moved network config params Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to

[m5-dev] changeset in m5: network: removed the unused network-wide latenc...

changeset f113f73dd494 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f113f73dd494 description: network: removed the unused network-wide latency param diffstat: src/mem/ruby/network/Network.cc | 1 - src/mem/ruby/network/Network.hh | 2 -- src/mem/ruby/network/Netwo

[m5-dev] changeset in m5: network: basic link bw for garnet and simple ne...

changeset 7c377f5162f8 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7c377f5162f8 description: network: basic link bw for garnet and simple networks This patch ensures that both Garnet and the simple networks use the bw value specified in the topology.

[m5-dev] changeset in m5: network: convert links & switches to first clas...

changeset 7226aebb77b4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7226aebb77b4 description: network: convert links & switches to first class C++ SimObjects This patch converts links and switches from second class simobjects that were virtually ignor

[m5-dev] changeset in m5: ruby: moved topology to the top network directory

changeset 73089f793a0a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=73089f793a0a description: ruby: moved topology to the top network directory Moved the Topology class to the top network directory because it is shared by both the simple and Garnet ne

[m5-dev] changeset in m5: garnet: cleaned up flexible network header file

changeset 2284cec55ef4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=2284cec55ef4 description: garnet: cleaned up flexible network header file diffstat: src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc | 2 -- 1 files changed, 0 insertions(+), 2 deleti

[m5-dev] changeset in m5: ruby: removed dated comment in SimpleNetwork

changeset 779d775abc11 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=779d775abc11 description: ruby: removed dated comment in SimpleNetwork diffstat: src/mem/ruby/network/simple/SimpleNetwork.hh | 34 1 files changed, 0 insertions(+), 34

Re: [m5-dev] Review Request: debug: fix help output

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[m5-dev] Review Request: debug: fix help output

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/666/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] changeset in m5: event: fix PythonEvent

changeset f2ec56fd42c0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f2ec56fd42c0 description: event: fix PythonEvent order of %includes since they matter for this case diffstat: src/python/swig/event.i | 4 +++- 1 files changed, 3 insertions(+), 1 deletions

Re: [m5-dev] Problem with LLDT on x86?

To clarify, by "make the switch" I mean replacing tr with tsl. Also, thanks again for another very high quality bug report. Gabe On 04/27/11 12:56, Gabe Black wrote: > There's a good chance the implementation was copied from LTR and not > completely updated. Please go ahead and make the switch, a

[m5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simp